Active HIGH / Active LOW

Hi,
There chips with the mixture of Active HIGH and Active LOW signals. Is
there any pros and cons of each levels? OR it simply choice of
designers / manufacturers?

Thanks in advance.

Regards,
Muthu

 

[glen herrmannsfeldt]

muthusnv@rediffmail.com wrote:

There chips with the mixture of Active HIGH and Active LOW signals. Is
there any pros and cons of each levels? OR it simply choice of
designers / manufacturers?

I believe for TTL there is some advantage to active low for
enables and such. TTL has much better current sinks than
current sources. I don't believe the advantage is as big,
if any, for CMOS but may have been kept for backward
compatibility reasons.

-- glen

 

[CWatters]

<muthusnv@rediffmail.com> wrote in message
news:1107206334.599924.199870@c13g2000cwb.googlegroups.com...

Hi,
There chips with the mixture of Active HIGH and Active LOW signals.

OR it simply choice of designers / manufacturers?

Yes the designer can define a signal to be active High or active Low - it's
his choice.

However... In general P type devices switch slower than N type. This means
that many devices have slightly different rise and fall times - eg the fall
time 5V->0V is faster than the rise time 0V->5V. This means that if you need
a fast edge for a signal (lets call it a "Ready" signal) then you use the
falling edge because thats faster. Therefore its natural to define Ready =
True = 0V. That makes it an Active Low signal.

 

[CWatters]

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:ctm8dm$vib$1@gnus01.u.washington.edu...

muthusnv@rediffmail.com wrote:

There chips with the mixture of Active HIGH and Active LOW signals. Is
there any pros and cons of each levels? OR it simply choice of
designers / manufacturers?

I believe for TTL there is some advantage to active low for
enables and such. TTL has much better current sinks than
current sources. I don't believe the advantage is as big,
if any, for CMOS but may have been kept for backward
compatibility reasons.

I may be out of date but... it used to be the case that P type devices were
roughly half as fast as N type. They got the edges symetrical in CMOS logic
families by making the P channel FET twice the size of the N channel FET.