Welcome Notice

Register Log in

Active-HDL issues with another VHDL-2008 construct...

R

Rick C

Guest
CASE? and \'-\' as a wildcard. It\'s part of the standard. case? pretty much has one purpose as far as I know, to accept \'-\' as a wildcard. Yet it rejects my code... :(

# KERNEL: Fatal Error: Don\'t care (\'-\') value in the matching select/case statement expression.

procedure Cmnd_Parse (
Command : in unsigned(8 downto 0);
Right_Left : in String;
Cmnd_Time : in time ) is
begin
case? Command is
when 9x\"000\" =>
assert false report Right_Left & \" - NOP with enable detected\";
when 9x\"001\" =>
assert false report Right_Left & \" - Clear Display command\";
when 9x\"002\" =>
assert false report Right_Left & \" - Return Home command\";
when b\"0000001--\" =>
....

There are a number of matching expressions with the wildcard \'-\' after this.

This has got to be an issue with the simulator, right? I guess I can try a test case that isn\'t so large, but this will be the second feature I\'ve found that Aldec doesn\'t support so well.

I hate to rip out all this code, but it looks like I\'ll have to replace it with IF statements and they will work better comparing from the high end down, so the order of comparisons will be opposite ... lots of editing. Fun...

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
 
R

Rick C

Guest
On Friday, October 30, 2020 at 3:41:22 AM UTC-4, Rick C wrote:
CASE? and \'-\' as a wildcard. It\'s part of the standard. case? pretty much has one purpose as far as I know, to accept \'-\' as a wildcard. Yet it rejects my code... :(

# KERNEL: Fatal Error: Don\'t care (\'-\') value in the matching select/case statement expression.

procedure Cmnd_Parse (
Command : in unsigned(8 downto 0);
Right_Left : in String;
Cmnd_Time : in time ) is
begin
case? Command is
when 9x\"000\" =
assert false report Right_Left & \" - NOP with enable detected\";
when 9x\"001\" =
assert false report Right_Left & \" - Clear Display command\";
when 9x\"002\" =
assert false report Right_Left & \" - Return Home command\";
when b\"0000001--\" =
...

There are a number of matching expressions with the wildcard \'-\' after this.

This has got to be an issue with the simulator, right? I guess I can try a test case that isn\'t so large, but this will be the second feature I\'ve found that Aldec doesn\'t support so well.

I hate to rip out all this code, but it looks like I\'ll have to replace it with IF statements and they will work better comparing from the high end down, so the order of comparisons will be opposite ... lots of editing. Fun...
I seem to get a lot of responses to my posts in stackexchange, particularly from Brian Drummond. He has indicated the problem is not my code, but a number of tools still fail this simple exercise even though they appear to support case? So the wild card \'-\' is to be avoided when portability of code is important even if the code runs with your tools.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
 
J

Jim Lewis

Guest
Case? does not allow the targets to overlap. To fully access correctness or not
with your code would require the rest of the code.

> # KERNEL: Fatal Error: Don\'t care (\'-\') value in the matching select/case statement expression.
This seems to imply that during simulation, the \"Command\" input has a\'-\' in it, which is an
error in your code.

From 1076-2008:
\"For a matching case statement in which the expression is of type STD_ULOGIC, or an array type whose
element type is STD_ULOGIC, it is an error if the value of the expression is the scalar value \'–\' or an array
value containing \'–\' as an element.\"

Verilog does not have this sort of a check by the language and it is a disaster for them.

Run your simulation, single step and observe the value of Command that makes it stop.
That will help you confirm this.

Best Regards,
Jim
 
R

Rick C

Guest
On Wednesday, November 4, 2020 at 8:58:36 PM UTC-5, Jim Lewis wrote:
Case? does not allow the targets to overlap. To fully access correctness or not
with your code would require the rest of the code.
Thanks for your reply. Yeah, the code is gone so I could get something to work. There was no overlapping. The \"commands\" are essentially priority encoded or whatever you want to call it as each command is defined by the first \'1\' from the left. So commands are \"00000001\", \"0000001-\", \"000001--\", etc. No overlapping. I ended up reworking it as IF command(7) = \'1\'.... ELSIF command(6) = \'1\'... ELSIF command(5) = \'1\'... ect.

The case? would have been less typing, maybe, but certainly more clear I think. 6 vs. half dozen I guess. Actually, I\'m just disappointed that there are still bugs in VHDL-2008 features after 12 friggin years!


# KERNEL: Fatal Error: Don\'t care (\'-\') value in the matching select/case statement expression.
This seems to imply that during simulation, the \"Command\" input has a\'-\' in it, which is an
error in your code.

From 1076-2008:
\"For a matching case statement in which the expression is of type STD_ULOGIC, or an array type whose
element type is STD_ULOGIC, it is an error if the value of the expression is the scalar value \'–\' or an array
value containing \'–\' as an element.\"
No, the input expression has no \'-\' in it. That value comes from some logic driven by a state machine. Possibly a \'X\' or \'U\' would appear at time 0, but not much chance of a \'-\' being generated from synthesizable logic. The CASE? is in the test bench code that is checking the commands that are sent by the synthesized logic.


Verilog does not have this sort of a check by the language and it is a disaster for them.

Run your simulation, single step and observe the value of Command that makes it stop.
That will help you confirm this.
I think this error is showing up at time 0, not sure. Actually, probably not. I think there is a wait for a falling edge, so not time zero I guess. The process would be run, but not this code. I should generate a test case, but I tried reporting another error to Aldec and got the \"talk to your FPGA vendor, it\'s their code now\" stiff arm and Lattice was polite but has not responded following the initial contact.

Bottom line is not much point in preparing a test case if they don\'t want to hear about it.

When they talk about \"expression is of type STD_ULOGIC\" I assume they include any closely related types like std_logic and arrays of same like unsigned? VHDL has so many rules it is hard to remember all the rules and terms and just everything. Maybe I need to retire to Florida.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209
 
Toggle Sidebar

Welcome to EDABoard.com

Sponsor

Top