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Dương Dương
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY accumulator IS
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
set : IN STD_LOGIC;
data_in : IN SIGNED(7 DOWNTO 0);
enable : IN STD_LOGIC;
accumulator_out : OUT SIGNED(11 DOWNTO 0));
END ENTITY accumulator;
ARCHITECTURE beh OF accumulator IS
SIGNAL accumulator_reg : SIGNED(11 DOWNTO 0);
BEGIN -- ARCHITECTURE beh
accumulator_proc : PROCESS (clk, rst_n, set, enable) IS
BEGIN -- PROCESS accumulator_proc
if rst_n = \'0\' then
accumulator_reg <= (OTHERS => \'0\');
elsif rst_n = \'1\' and set = \'1\' then
accumulator_reg <= \"0000\" & data_in;
elsif rst_n = \'1\' and set = \'0\' and enable = \'1\' then
accumulator_reg <= accumulator_reg + data_in;
end if;
END PROCESS accumulator_proc;
accumulator_out <= accumulator_reg;
END ARCHITECTURE beh;
My rst_n signal is synchronous or asynchronous.
Help me design this signal in the remaining way. Thanks
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY accumulator IS
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
set : IN STD_LOGIC;
data_in : IN SIGNED(7 DOWNTO 0);
enable : IN STD_LOGIC;
accumulator_out : OUT SIGNED(11 DOWNTO 0));
END ENTITY accumulator;
ARCHITECTURE beh OF accumulator IS
SIGNAL accumulator_reg : SIGNED(11 DOWNTO 0);
BEGIN -- ARCHITECTURE beh
accumulator_proc : PROCESS (clk, rst_n, set, enable) IS
BEGIN -- PROCESS accumulator_proc
if rst_n = \'0\' then
accumulator_reg <= (OTHERS => \'0\');
elsif rst_n = \'1\' and set = \'1\' then
accumulator_reg <= \"0000\" & data_in;
elsif rst_n = \'1\' and set = \'0\' and enable = \'1\' then
accumulator_reg <= accumulator_reg + data_in;
end if;
END PROCESS accumulator_proc;
accumulator_out <= accumulator_reg;
END ARCHITECTURE beh;
My rst_n signal is synchronous or asynchronous.
Help me design this signal in the remaining way. Thanks