T
Torsten Bitterlich
Guest
Hi there,
what I want to do is to implement a function or procedure within a
entity, which can be accessed from the outside of the belonging entity.
I need this to get some status information at the end of the simulation
out of a component. Since the component doesn't know about the end of
the simulation, the testbench should access this function to do the
task. Is this possible with VHDL or is there a clean way to implement
this behaviour?
Thanks for any help,
Torsten Bitterlich
what I want to do is to implement a function or procedure within a
entity, which can be accessed from the outside of the belonging entity.
I need this to get some status information at the end of the simulation
out of a component. Since the component doesn't know about the end of
the simulation, the testbench should access this function to do the
task. Is this possible with VHDL or is there a clean way to implement
this behaviour?
Thanks for any help,
Torsten Bitterlich