About fpga board

Hi

I am working with group research in college
We work on fpga board we finish coding on matlab now we want convert this code to vhdl i knew about the feature that matlab allow me to convert but as what i read it is for small code or not?
i dont have any previous knowledge about this board also i am not dealing a lot with assimbly language,

so i want ask
How long it will take to learn vhdl virelog language? And is there any tool or way could help to convert code?

 

[rickman]

On 7/26/2015 11:32 PM, abdrhblushi@gmail.com wrote:

Hi

I am working with group research in college We work on fpga board we
finish coding on matlab now we want convert this code to vhdl i knew
about the feature that matlab allow me to convert but as what i read
it is for small code or not? i dont have any previous knowledge about
this board also i am not dealing a lot with assimbly language,

so i want ask How long it will take to learn vhdl virelog language?
And is there any tool or way could help to convert code?

Verilog and VHDL are two separate HDLs (Hardware Description Language)
for the same job. Asking how long it will take to learn them is like
asking, "how long is a piece of string?" That will depend on you.

Is your class a coding class or a hardware design class? If the purpose
is to learn an HDL what are you having trouble with? If the purpose is
to learn to design hardware, then why do you need to learn an HDL?
Can't Matlab pump out an HDL file?

--

Rick

 

[glen herrmannsfeldt]

abdrhblushi@gmail.com wrote:

I am working with group research in college
We work on fpga board we finish coding on matlab now we
want convert this code to vhdl i knew about the feature that matlab
allow me to convert but as what i read it is for small code or not?
i dont have any previous knowledge about this board also i am
not dealing a lot with assimbly language,

Why do you want to convert to VHDL for an FPGA?

You don't say at all what kind of algorithm it is, which can make
a big difference. Usually you do it to make it faster, but you
don't say how fast it needs to be.

so i want ask
How long it will take to learn vhdl virelog language?

If you understand digital logic, have wired up TTL gates to
make working systems, then it won't take very long,

If you haven't, then a long time.

> And is there any tool or way could help to convert code?

There might be, but you don't want to use it if it does.

FPGA implementations of algorithms are usually different from
Matlab implementations. If you don't understand the details
of the algorithms, there is no use in doing it.

(Note that you can implement a processor in the FPGA, then
run Matlab on that processor. That likely isn't the reason
to use the FPGA or VHDL.)

-- glen

 

The story was that we had AES(advance encryption standard) algorithm and we want to put it in fpga board to use it in our college, the problem now i try to implement some example of code to test the board but i faced difficulty and i felt that i am on the middel of the ocean and i forget to swim. I am thinking to take courses but it not available in my country or college, and i have to finish the work within two month

 

[glen herrmannsfeldt]

abdrhblushi@gmail.com wrote:

The story was that we had AES(advance encryption standard)
algorithm and we want to put it in fpga board to use it in
our college, the problem now i try to implement some example
of code to test the board but i faced difficulty and i felt
that i am on the middel of the ocean and i forget to swim.

It is usual to feel lost at the beginning of learning something
new, so don't worry about that.

But you do need to learn to think about wires and signals,
if you haven't before. You can do this separate from
learning VHDL.

Have you done any electronic projects before?

Analog or digital?

I am thinking to take courses but it not available in my
country or college, and i have to finish the work within
two month

There should be some Coursera courses that cover enough.

-- glen

 

[rickman]

On 7/27/2015 8:41 PM, abdrhblushi@gmail.com wrote:

The story was that we had AES(advance encryption standard) algorithm
and we want to put it in fpga board to use it in our college, the
problem now i try to implement some example of code to test the board
but i faced difficulty and i felt that i am on the middel of the
ocean and i forget to swim. I am thinking to take courses but it not
available in my country or college, and i have to finish the work
within two month

Rather than fight the FPGA which can be a PITA, run your code on the
simulator. You should be able to input and output files for the data
you want to decrypt/encrypt. You can watch every value in every part of
the design without needing to place probes. If the simulation works ok
then you need to look for issues related to the possible errors that
won't show in simulation. These errors are checked for in other ways or
are usually avoided by paying attention to the few specific details
involved such as clock domain crossing. But the simulation is the
starting point.

A friend used to have the email tag line, "If the dead in tombs are
entombed, are the dead in crypts encrypted?"

--

Rick

 

There is no way back so i will make more effort to learn it in two months, what are your advices and guidelines for me? I will be thankful

 

[glen herrmannsfeldt]

abdrhblushi@gmail.com wrote:

There is no way back so i will make more effort to learn it
in two months, what are your advices and guidelines for me?
I will be thankful

What have you done before?

It is hard to say much without knowing that.

Have you built any electronic circuits? Even simple ones?

Have you worked at all with TTL circuits?

-- glen

 

I didn't do any thaings of what you said, but i am ready to do any things to be in the true way to learn it

 

I am good in java
I understand the logic of it very well

So i will do what you said then i will return to show you the result and what i understand, now i have final exam after finishing i will try it..

Thank you very much for your help

 

[rickman]

On 8/1/2015 2:53 PM, abdrhblushi@gmail.com wrote:
> I didn't do any thaings of what you said, but i am ready to do any things to be in the true way to learn it

Are you familiar with programming languages? Which ones and how much?

A software designer came to this group once asking for help writing a
"Hello world" program in HDL. Many of us told him it would be a
difficult job if he didn't learn to "think" in hardware. I spent some
time coaching him a bit and he had no trouble at all doing what he
needed to do. Turns out you can write HDL similar to software as long
as you observe a few basic rules. So this might not be such a difficult
task if you can get Matlab to spit out some working code like C for
example.

Doesn't Matlab spit out an HDL though? I'm pretty sure I've heard of
that. First think you need to do is to pick a starting point. I think
working from the Matlab code is the last option you should pursue.

--

Rick

 

[rickman]

On 8/1/2015 3:57 PM, abdrhblushi@gmail.com wrote:

I am good in java
I understand the logic of it very well

So i will do what you said then i will return to show you the result and what i understand, now i have final exam after finishing i will try it..

Showing me Java won't mean much to me as I don't write or read it. I am
pretty sure MatLab will translate your Matlab code to an HDL. Why not
use that for a first pass. We can help you massage that code to make it
work the way you want I expect. Likely easier than trying to teach you
HDL from your understanding of Java.

--

Rick

 

It is good idea i will send all codes that i want to convert to your email, please send it for me,
My email: abdrhblushi@gmail.com

With regards

 

Matlab code

 

[rickman]

On 8/4/2015 7:08 AM, abdrhblushi@gmail.com wrote:

It is good idea i will send all codes that i want to convert to your email, please send it for me,
My email: abdrhblushi@gmail.com

What type of code do you have?

--

Rick

 

[rickman]

On 8/4/2015 4:07 PM, abdrhblushi@gmail.com wrote:
> Matlab code

Have you asked Matlab to convert your design to an HDL yet?

--

Rick

 

[Brian Drummond]

On Tue, 04 Aug 2015 19:47:30 -0400, rickman wrote:

On 8/4/2015 4:07 PM, abdrhblushi@gmail.com wrote:
Matlab code

Have you asked Matlab to convert your design to an HDL yet?

That requires an expensive additional tool, strangely called called "HDL
Coder", and last time I looked it generated hilariously awful VHDL. It's
probably easier to convert from Matlab to VHDL by hand that work with HDL
Coder's output...

-- Brian

 

[glen herrmannsfeldt]

Brian Drummond <brian@shapes.demon.co.uk> wrote:

On Tue, 04 Aug 2015 19:47:30 -0400, rickman wrote:
(snip)
Have you asked Matlab to convert your design to an HDL yet?

That requires an expensive additional tool, strangely called called "HDL
Coder", and last time I looked it generated hilariously awful VHDL. It's
probably easier to convert from Matlab to VHDL by hand that work with HDL
Coder's output...

That is what I would expect.

Well, there is an easy way, which is to generate code for a soft
processor in ROM, and then generate VHDL for the processor.

Many years ago, I had some perl programs that ran too slow
(1 MB/min). I found a perl2c converter, converted to C, and
found it was just as slow. The converter generates the internal
code that perl uses, and the interpreter for that code.

Often the useful hardware implementation of an algorithm is
completely different from the usual software implementations.
It is unusual for tools to figure that out.

-- glen

 

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:

(snip, I wrote)

Often the useful hardware implementation of an algorithm is
completely different from the usual software implementations.
It is unusual for tools to figure that out.

That is pretty obvious if you give it a bit of thought. A CPU running
software is a *HUGE* finite state machine (FSM) with the memory
containing the majority of the state along with the fewer registers in
the CPU. The memory contents are all accessed through a very large
multiplexer and operations on this FSM are time multiplexed and
controlled by a program stored in memory.

In one of these newsgroups, a year or two ago, I called
microprocessors the biggest waste of transistors, for this reason.

These days, billions of transistors to funnel data through a
(small number) of thousand transistor ALUs, and back out again.

With systolic arrays, it is often not hard to chain together a
large number of arithmetic blocks, each operating every clock cycle.

In an FPGA or ASIC the logic can all be designed in parallel with the
much less happening sequentially. The design could be done in the same
way with the very large multiplexers. The program can be done with
logic rather than a stored program, but the access to the large FSM
still requires a lot of multiplexers. So while it is possible to
duplicate the actual CPU in an FPGA, it is seldom the best way to
utilize an FPGA. The same problem can be implemented with a lot fewer
gates by tailoring the algorithm to take advantage of the parallel
nature of the FPGA and only implementing the specific data paths
required by the problem. The generic CPU gains efficiency by the
repetition of the regular arrays in memory which can be made both small
and cheap but only with a sequential algorithm.

There is the assumption that some things can be done in parallel,
but yes.

-- glen

 

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:

(snip, I wrote)

In one of these newsgroups, a year or two ago, I called
microprocessors the biggest waste of transistors, for this reason.

These days, billions of transistors to funnel data through a
(small number) of thousand transistor ALUs, and back out again.

A very efficient use of the ALU while wasting so many elements in the
memory mux. In reality the comparison is cost vs. the application
needs. Often the things that need to be done can be done sequentially,
even when they appear to be done in parallel. So while an FPGA may more
fully utilize the transistor count, it often wastes the performance
capabilities of those transistors while a CPU more fully exploits them.

Yes. I was thinking about using either a microprocessor or FPGA
to build a digital clock. In either case, a large fraction of the
time there is nothing to do. (That is, relative to the switch rate.)

Our home computers spend most of the time not doing anything useful.

With systolic arrays, it is often not hard to chain together a
large number of arithmetic blocks, each operating every clock cycle.

In an FPGA or ASIC the logic can all be designed in parallel with the
much less happening sequentially. The design could be done in the same
way with the very large multiplexers. The program can be done with
logic rather than a stored program, but the access to the large FSM
still requires a lot of multiplexers.

(snip)

There is the assumption that some things can be done in parallel,
but yes.

Perhaps "parallel" is not the best term. In hardware they would be
called concurrent. That doesn't mean the output of one isn't the input
of another. It just means the two operations are working at the same
time on separate hardware whether or not they are actually doing
anything useful all the time.

There are many ways to compare solutions to computing needs. Many like
the familiarity of CPUs (every problem looks like a nail) while others
like the flexibility of FPGAs (Swiss army knife).

Interesting way to say it.

-- glen