6 bit things...

[Mike Monett]

Jeroen Belleman <jeroen@nospam.please> wrote:

> On 2022-08-06 19:52, John Larkin wrote:

[...]

My favorite phase detector is a single d-flop. Clock from received
data, poke the local VCXO square wave into D.

It makes an early/late decision every data rising edge, and can
produce picosecond time alignment and picosecond jitter.

It\'s basically infinite gain and immune to analog errors. A
differential ECL flop is best, like NB7V52.


Infinite (OK, very large) gain around the lock target and zero
gain elsewhere. Not something you really want in a well behaved
loop. You really want constant loop gain.

Jeroen Belleman

A single d-flop is a phase detector, not a frequency detector. It shares
the same lock characteristic with an XOR and a double balanced mixer,
although the XOR and DBM are quadrature detectors, where the d-flop is in
phase.

It has the highly desirable property of retaining the same gain on
harmonics, where the XOR and double balanced mixer both lose gain.

It takes the addition of a second d-flop and a feedback gate to create a
frequency/phase detector. However, it will no longer work on harmonics.

For more information on quadrature detectors, see \"Operation of Phase
Comparator PC1\" on page 9 of

https://www.ti.com/lit/an/scha003b/scha003b.pdf





--
MRM

 

[Ricky]

On Saturday, August 6, 2022 at 2:19:21 PM UTC-4, Joe Gwinn wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things..

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010
Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

What\'s needed is to choose a pattern that will also ensure correct
framing in an arbitrary random string of one and zero symbols. This
is a slightly stronger requirement than orthogonal: The symbols must
be a good synch pattern as well. With only two kinds of symbol, it
ought to be possible, given a sufficiently long pattern.

No, the pattern Larkin describes will provide accurate data at all times. While the PLL will produce the 4x clock, there is no data clock without examining the recovered data using the XOR gate, as he describes. By monitoring the output of that \"detector\", there will be a transition when the data changes.

So with initially, all 1 data, the decode will produce 1s on all 4x clock transitions. However, there is no way to detect the data clock, until the data changes yielding an edge in the data output, showing the data boundary in the 4x clock domain, and showing the alignment of the 1x data.

This is not really an advantage over other schemes which also depend on the data changing to obtain alignment, such as simple Manchester.

The method I described previously, with the pattern of 1 1 d0 \\d0 0 0 d1 \\d1 provides the same data density, and will synchronize unambiguously without regard to the data, because of the changing sync pattern. It also provides a data clock.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

 

[John Larkin]

On Sat, 6 Aug 2022 14:28:10 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin wrote:
On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spamme@not.com
wrote:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com
jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?


which means that a simple running decoder can mis-frame the clumps.

won\'t you have that problem with all possible ways of using 4 bit?

MFM coding is DC balanced and easy to encode. It is hard to decode:

https://en.wikipedia.org/wiki/Modified_frequency_modulation

It requires a PLL with zero deadband. I invented the first zero deadband
PFD in 1970, and Memorex patented it. It is shown on page 3 of my \'234
patent:

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102
34.pdf

My favorite phase detector is a single d-flop. Clock from received
data, poke the local VCXO square wave into D.

It makes an early/late decision every data rising edge, and can
produce picosecond time alignment and picosecond jitter.

It\'s basically infinite gain and immune to analog errors. A
differential ECL flop is best, like NB7V52.


$18 in hundreds. Got a second fave for us picosecond proles?

Cheers

Phil Hobbs

Well, you can use a pokey flop like MC10EP51, or degrade yourself and
use a 1 ns cmos flop, like NC7SV74, which will set you back about 13
cents. But give up diff data+diff clock.





--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Sat, 06 Aug 2022 22:32:11 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 2022-08-06 19:52, John Larkin wrote:
On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spamme@not.com
wrote:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com
jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?


which means that a simple running decoder can mis-frame the clumps.

won\'t you have that problem with all possible ways of using 4 bit?

MFM coding is DC balanced and easy to encode. It is hard to decode:

https://en.wikipedia.org/wiki/Modified_frequency_modulation

It requires a PLL with zero deadband. I invented the first zero deadband
PFD in 1970, and Memorex patented it. It is shown on page 3 of my \'234
patent:

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102
34.pdf

My favorite phase detector is a single d-flop. Clock from received
data, poke the local VCXO square wave into D.

It makes an early/late decision every data rising edge, and can
produce picosecond time alignment and picosecond jitter.

It\'s basically infinite gain and immune to analog errors. A
differential ECL flop is best, like NB7V52.


Infinite (OK, very large) gain around the lock target and zero
gain elsewhere. Not something you really want in a well behaved
loop. You really want constant loop gain.

Jeroen Belleman

What I want is a PLL that is time locked to a few picoseconds
long-term and has about a ps of RMS jitter.

https://www.highlandtechnology.com/DSS/V880DS.shtml

https://www.dropbox.com/s/rb0fasr1flvvk51/NIF_Award.jpg?raw=1

The d-flop phase detector annoys some people, but nothing else comes
close.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Sun, 7 Aug 2022 00:49:42 -0000 (UTC), Mike Monett <spamme@not.com>
wrote:

Jeroen Belleman <jeroen@nospam.please> wrote:

On 2022-08-06 19:52, John Larkin wrote:

[...]

My favorite phase detector is a single d-flop. Clock from received
data, poke the local VCXO square wave into D.

It makes an early/late decision every data rising edge, and can
produce picosecond time alignment and picosecond jitter.

It\'s basically infinite gain and immune to analog errors. A
differential ECL flop is best, like NB7V52.


Infinite (OK, very large) gain around the lock target and zero
gain elsewhere. Not something you really want in a well behaved
loop. You really want constant loop gain.

Jeroen Belleman

A single d-flop is a phase detector, not a frequency detector.

Yes. PLL.

It shares

the same lock characteristic with an XOR and a double balanced mixer,
although the XOR and DBM are quadrature detectors, where the d-flop is in
phase.

But the dflop gain is absurdly higher than an XOR or a mixer. An XOR
with microvolt offsets makes picoseconds of time error and 1/f noise.

Diode tempco in a mixer is worse.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Joe Gwinn]

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

 

[John Larkin]

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

The decoder is a 3-bit shift register. Xnor the first and last bits.

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Ricky]

On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjla...@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode.. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn
The decoder is a 3-bit shift register. Xnor the first and last bits.

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use. Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010 while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a \"good\" reference to align the 1x clock to.

Using the pattern 1 1 d1 \\d1 0 0 d2 \\d2 gets around this limitation and is still easy to generate, easy to decode and provides references to align the clock no matter what the data is or whether it changes. This decoder doesn\'t even require a separate PLL, clock timing being embedded in the data stream. A <2x clock will be able to provide a clock enable for data samples.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 18.18.07 UTC+2 skrev Joe Gwinn:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjla...@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.
I guess I\'m not visualizing the specific circuit used.

I was bored so I drew it up in spice, the missing bit is generating you receiver clock from the data and resolving the half bit timing uncertainty that you can\'t tell where a the 4 bit 1010 starts in a long string of 1010101010101, so you\'ll need at least one 1001 to sync up
and that was what discussion was mostly about

Version 4
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WIRE 544 224 480 224
WIRE 80 288 80 224
WIRE 800 288 800 208
WIRE 800 288 80 288
WIRE 80 304 80 288
WIRE 1840 320 1840 208
WIRE 2096 320 2096 208
WIRE 2096 320 1840 320
WIRE 2336 320 2336 208
WIRE 2336 320 2096 320
FLAG 80 384 0
FLAG -544 -352 0
FLAG 1840 400 0
FLAG 1712 -32 0
FLAG 400 -144 ADC_CLK
FLAG 560 -256 ADC_Dp
FLAG 560 -208 ADC_Dn
FLAG 2880 96 DATA_OUT
SYMBOL Digital\\\\dflop 240 128 R0
WINDOW 3 8 12 Left 2
SYMATTR Value td=1n
SYMATTR InstName A1
SYMBOL voltage 80 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(.5 .5 80e6)
SYMBOL bv -544 -464 R0
WINDOW 3 52 61 Left 2
SYMATTR Value V=RAND(time*1e8)+0.25
SYMATTR InstName B1
SYMBOL Digital\\\\dflop 240 -80 R0
WINDOW 3 8 12 Left 2
SYMATTR Value td=1n
SYMATTR InstName A2
SYMBOL Digital\\\\dflop -336 -304 R0
WINDOW 3 8 12 Left 2
SYMATTR Value td=1n
SYMATTR InstName A3
SYMBOL Digital\\\\dflop 944 112 R0
WINDOW 3 8 12 Left 2
SYMATTR Value td=1n
SYMATTR InstName A4
SYMBOL Digital\\\\and 576 128 R0
SYMATTR InstName A5
SYMBOL Digital\\\\and 576 -80 R0
SYMATTR InstName A6
SYMBOL Digital\\\\dflop 1968 112 R0
WINDOW 3 8 12 Left 2
SYMATTR Value td=1n
SYMATTR InstName A8
SYMBOL Digital\\\\dflop 2208 112 R0
WINDOW 3 8 12 Left 2
SYMATTR Value td=1n
SYMATTR InstName A9
SYMBOL Digital\\\\dflop 2432 112 R0
WINDOW 3 8 12 Left 2
SYMATTR Value td=1n
SYMATTR InstName A10
SYMBOL Digital\\\\xor 2768 16 R0
SYMATTR InstName A11
SYMBOL voltage 1840 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(.5 .5 80e6 15n 0)
SYMBOL Digital\\\\and 720 32 R0
SYMATTR InstName A7
SYMBOL cap 1280 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage 1712 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0.5
SYMBOL res 1632 64 R0
SYMATTR InstName R2
SYMATTR Value 1k
TEXT 1200 -504 Left 2 !.tran 10u
TEXT -400 -472 Left 2 ;ADC sim
TEXT 880 -440 Left 2 ;Transmitter
TEXT 1480 -448 Left 2 ;Reciever
RECTANGLE Normal 1088 432 -64 -496 2
RECTANGLE Normal -624 -496 -144 -144 2
RECTANGLE Normal 3040 432 1440 -496 2

 

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:

On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjla...@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn
The decoder is a 3-bit shift register. Xnor the first and last bits.

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.
This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use. Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010 while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a \"good\" reference to align the 1x clock to.

Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing doesn\'t really matter

 

[Ricky]

On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:

søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjla...@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn
The decoder is a 3-bit shift register. Xnor the first and last bits.

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.
This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use. Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010 while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a \"good\" reference to align the 1x clock to.

Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing doesn\'t really matter

That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \\d1 0 0 d2 \\d2 pattern doesn\'t have this problem and is still simple to encode and decode.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 20.49.12 UTC+2 skrev Ricky:

On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:
søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjla...@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla....@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate..

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn
The decoder is a 3-bit shift register. Xnor the first and last bits..

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d..
Any 0 sees a \\d.
This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use. Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010 while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a \"good\" reference to align the 1x clock to.

Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing doesn\'t really matter
That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \\d1 0 0 d2 \\d2 pattern doesn\'t have this problem and is still simple to encode and decode.

stutter or even syncing might not even be an important, the uncertainty is 25ns at 20MHz and after decimation by 256 as in the datasheet
the sample rate is 78.125kHz or 128us

25ns is ~8m at the speed of light

 

[Ricky]

On Sunday, August 7, 2022 at 3:09:31 PM UTC-4, lang...@fonz.dk wrote:

søndag den 7. august 2022 kl. 20.49.12 UTC+2 skrev Ricky:
On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:
søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjla...@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn
The decoder is a 3-bit shift register. Xnor the first and last bits.

Or draw a long string of 4-bit frames, encoding various 1s and 0s.. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.
This circuit requires a clock which will be 4x the actual data rate.. It then produces a data stream and a 1x clock still needs to be generated.. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use. Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010 while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a \"good\" reference to align the 1x clock to.

Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing doesn\'t really matter
That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \\d1 0 0 d2 \\d2 pattern doesn\'t have this problem and is still simple to encode and decode.

stutter or even syncing might not even be an important, the uncertainty is 25ns at 20MHz and after decimation by 256 as in the datasheet
the sample rate is 78.125kHz or 128us

25ns is ~8m at the speed of light

But sampling data when it is changing can cause missed bits and inserted bits, neither very useful.

That\'s why the 1x clock has to see the data changes, to know to sample on other edges of the 4x clock.

As I\'ve said any number of times, using a pattern of 1 1 d1 \\d1 0 0 d2 \\d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:

On Sunday, August 7, 2022 at 3:09:31 PM UTC-4, lang...@fonz.dk wrote:
søndag den 7. august 2022 kl. 20.49.12 UTC+2 skrev Ricky:
On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:
søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjla...@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn
The decoder is a 3-bit shift register. Xnor the first and last bits.

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.
This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use. Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010 while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a \"good\" reference to align the 1x clock to.

Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing doesn\'t really matter
That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \\d1 0 0 d2 \\d2 pattern doesn\'t have this problem and is still simple to encode and decode.

stutter or even syncing might not even be an important, the uncertainty is 25ns at 20MHz and after decimation by 256 as in the datasheet
the sample rate is 78.125kHz or 128us

25ns is ~8m at the speed of light
But sampling data when it is changing can cause missed bits and inserted bits, neither very useful.

That\'s why the 1x clock has to see the data changes, to know to sample on other edges of the 4x clock.

as long as the 4x is PLL\'ed to the data that\'s not an issue

As I\'ve said any number of times, using a pattern of 1 1 d1 \\d1 0 0 d2 \\d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

so like this ?

d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

what edge would you use?

 

[Ricky]

On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:

søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
As I\'ve said any number of times, using a pattern of 1 1 d1 \\d1 0 0 d2 \\d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

so like this ?

d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010

When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?


> d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are the only indicators of valid data. Any other pattern is misalignment.

This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.

> what edge would you use?

Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock enable is generated. I would need to know more about the circuit receiving the data to give details. It\'s not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don\'t recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it\'s buried in the thread somewhere.

--

Rick C.

++- Get 1,000 miles of free Supercharging
++- Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

søndag den 7. august 2022 kl. 23.32.13 UTC+2 skrev Ricky:

On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:
søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
As I\'ve said any number of times, using a pattern of 1 1 d1 \\d1 0 0 d2 \\d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

so like this ?

d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?

yes

d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are the only indicators of valid data. Any other pattern is misalignment.

This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.

yes that should work, encoding is a bit more effort if you have to do it in discrete logic

what edge would you use?
Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock
enable is generated.

ah, I wrongly assumed you\'d some how skip the pll and use the data as clock

I would need to know more about the circuit receiving the data to give details. It\'s not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don\'t recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it\'s buried in the thread somewhere.

afaict it goes into a decimator, so the whole thing could run on the pll clock, or the much slower output could be synchronized

 

[Ricky]

On Sunday, August 7, 2022 at 6:02:18 PM UTC-4, lang...@fonz.dk wrote:

søndag den 7. august 2022 kl. 23.32.13 UTC+2 skrev Ricky:
On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:
søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
As I\'ve said any number of times, using a pattern of 1 1 d1 \\d1 0 0 d2 \\d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

so like this ?

d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?

yes

d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are the only indicators of valid data. Any other pattern is misalignment.

This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.
yes that should work, encoding is a bit more effort if you have to do it in discrete logic

Encode is idiot simple. A 3 bit counter is decoded to send the appropriate bits at the appropriate time. Again, an 8 to 1 mux and an inverter does the job. Of course, the clock is 4x the actual data rate. In gates, I think an xor, and three, 2-input NANDs, will do the job. Might need an inverter, so four, 2-input NAND gates.

what edge would you use?
Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock
enable is generated.
ah, I wrongly assumed you\'d some how skip the pll and use the data as clock

You can. You have to use the logic output and watch for the enable to be asserted. However, because the logic is not race free, you need to design a circuit to reject glitches. But you have to have a clock to drive the shift register. If you use an arbitrary rate clock, it can be done, but the logic is a bit more. It\'s essentially a digital PLL.

I would need to know more about the circuit receiving the data to give details. It\'s not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don\'t recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it\'s buried in the thread somewhere.

afaict it goes into a decimator, so the whole thing could run on the pll clock, or the much slower output could be synchronized

Ok.

--

Rick C.

+++ Get 1,000 miles of free Supercharging
+++ Tesla referral code - https://ts.la/richard11209

 

[Joe Gwinn]

On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

The decoder is a 3-bit shift register. Xnor the first and last bits.

Meaning the outputs of stages 1 and 3, for a separation of two bits?

Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

XNOR will emit a One if the two inputs are the same, and Zero
otherwise. So either matched Zeros or matched Ones will yield a One.
..<https://en.wikipedia.org/wiki/XNOR_gate>

I have been playing with it, and I\'m not getting useful detection of
the sent MDATA bits. Perhaps I\'m doing something wrong?

This approach does not yield only one output bit per 4-bit input
symbol, instead getting large rafts of output bits, so it seems that
we still need to find the framing somehow to achieve the 4:1 bitrate
reduction.


More generally, the basic topology of a correlation receiver is a
tapped delay line feeding a pattern-matching function of some kind.

So a shift register feeding a XNOR gate is in fact a kind of
correlation receiver. Because it\'s implemented using purely digital
logic, it will not have much tolerance of noise.

However, in the proposed application, scattered decode errors probably
have little effect on the low-passed analog signal being transmitted,
which should be the case so long as the optical SNR is large.


However, if the same thing is instead implemented using an analog
integrate-and-dump scheme (or sampled equivalent), the tolerance of
noise is dramatically increased, and can approach matched-filter
optimum. Which is why it\'s done that way for Ethernet.

There is also a complicated tradeoff between dispersion (various
kinds) and attenuation with distance in the fiber. Basically, up to a
point, one can overcome distortion by providing added optical power or
more sensitive optical receivers. In Ethernet, transmit optical power
is limited to ensure eye safety, so the action is largely in receiver
design. (In telcomms, transmit power may be far larger.)




Joe Gwinn

 

[John Larkin]

On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:

On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

The decoder is a 3-bit shift register. Xnor the first and last bits.

Meaning the outputs of stages 1 and 3, for a separation of two bits?


Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

XNOR will emit a One if the two inputs are the same, and Zero
otherwise. So either matched Zeros or matched Ones will yield a One.
.<https://en.wikipedia.org/wiki/XNOR_gate

I have been playing with it, and I\'m not getting useful detection of
the sent MDATA bits. Perhaps I\'m doing something wrong?

This approach does not yield only one output bit per 4-bit input
symbol, instead getting large rafts of output bits, so it seems that
we still need to find the framing somehow to achieve the 4:1 bitrate
reduction.

I intend to lowpass filter it. I don\'t need a bit rate reduction.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Jasen Betts]

On 2022-08-06, Ricky <gnuarm.deletethisbit@gmail.com> wrote:

On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

This sequence is also pathological for continuous one data. You end up with 10101010 with no way to distinguish the frame bits from the data.

How would that matter? eventually it will resolve, and until then it
is all ones anyway, you might be off by a count of one, but coming
into the signal mid stream you are already starting from a bad position,
and this hasn\'t made it any worse than it would be if you could find
the frame start immediately. So just guess, if it turns out you were
wrong there\'s only one other choice.

This is raw delta-sigma data, so all bits are least signifigant, and
if you receive, missed, extra, or corrupted single bits it prpbably
won\'t have noticeable effect.

> There is nothing magical about the pattern 1 0 d \\d.

Yeah, for example FM coding gets you the same features in half as many timeslots.

--
Jasen.