528MHz clock level conversion

R

RobJ

Guest
I need to amplify a low-level 528MHz clock to an LVCMOS-level compatible
(i.e., 3.3V logic) single-ended clock. I have some control over the
low-level clock, but assume it's a 400mVpp sine wave. It is generated by a
Silicon Labs Si4133 synthesizer (IF output).

There are no LVTTL/LVCMOS buffers out there that can handle anywhere near
528MHz. I can get almost to the level I need using wideband transformers
from Mini-Circuits, but that causes large impedance changes across the
transformers and I still barely end up with 2Vpp. I would prefer an active
buffer using an Op Amp or transistor. The sine wave shape is not important
(i.e., a square wave output is fine), but I do need to preserve the duty
cycle as much as possible and minimize jitter. The system is nominally 50
Ohms (FR4 PCB traces) and the 3.3V clock load is a CMOS input buffer on an
IC.

Any suggestions would be appreciated.

Rob
 
John Larkin wrote:
An SN65LVDS2DBVB would probably work that fast. Technically, the input
common-mode range is 0.2 to 2.2, but they seem to work fine around
ground. I use them, basically, as fast, cheap comparators. The output
swings 3.3 volts in something outrageous like 420 ps. I'd suggest a
source terminator resistor in series with the output. Output-to-input
DC feedback could be used to servo the duty cycle to exactly 50%.

I've got a system with several of these, plus a lot more stuff, in the
signal chain and I'm getting overall jitter of a few ps RMS.

Or an opamp, THS4302 maybe.


John
Click to expand...
The SN65LVDS2 has the fastest LVTTL output rating I've seen, I think, and
I've looked at A LOT of diff to single-ended buffers. But it's still only
rated for 400MHz. May work but I'd have to bread board it first. The THS4302
looks like a winner, though. Its large-signal gain is flat way beyond
500MHz. Thanks for the help!

Rob
 
RobJ wrote:

John Larkin wrote:

An SN65LVDS2DBVB would probably work that fast. Technically, the input
common-mode range is 0.2 to 2.2, but they seem to work fine around
ground. I use them, basically, as fast, cheap comparators. The output
swings 3.3 volts in something outrageous like 420 ps. I'd suggest a
source terminator resistor in series with the output. Output-to-input
DC feedback could be used to servo the duty cycle to exactly 50%.

I've got a system with several of these, plus a lot more stuff, in the
signal chain and I'm getting overall jitter of a few ps RMS.

Or an opamp, THS4302 maybe.


John


The SN65LVDS2 has the fastest LVTTL output rating I've seen, I think, and
I've looked at A LOT of diff to single-ended buffers. But it's still only
rated for 400MHz. May work but I'd have to bread board it first.
Click to expand...
Breadboard ?
A lof of speed may be lost due to lacking design.
A few nH here another few pF there ...

Rene
 
RobJ wrote:
There are no LVTTL/LVCMOS buffers out there that can handle anywhere near
528MHz.
Click to expand...
That's what makes your requirement suspicious. You have mismanaged your
component configuration somewhere along the way. There are synthesizer
IC's that just produce 3.3V CMOS clock levels at 500MHz.
 
Fred Bloggs wrote:
RobJ wrote:

There are no LVTTL/LVCMOS buffers out there that can handle anywhere
near 528MHz.

That's what makes your requirement suspicious. You have mismanaged
your component configuration somewhere along the way. There are
synthesizer IC's that just produce 3.3V CMOS clock levels at 500MHz.
Click to expand...
I'm a consultant developing proto/eval boards for a wireless chip company.
Some things are out of my control. The RF synthesizer that generates the
528MHz IF output also generates RF outputs that are needed in the system.
Sometimes you just have to make do with what you have. This is one of those
times.

Rob
 
On Fri, 31 Dec 2004 12:37:00 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

RobJ wrote:

There are no LVTTL/LVCMOS buffers out there that can handle anywhere near
528MHz.

That's what makes your requirement suspicious. You have mismanaged your
component configuration somewhere along the way. There are synthesizer
IC's that just produce 3.3V CMOS clock levels at 500MHz.
Click to expand...

Never miss an opportunity for an insult, huh Fred?

I guess everybody who ever uses chips with different I/O level specs
is an idiot.

John
 
RobJ wrote...
This is a weird situation.
Here's the history of how it got to this point.
Click to expand...
All I can say is, sheesh!


--
Thanks,
- Win
 
On 31 Dec 2004 12:29:10 -0800, Winfield Hill
<hill_a@t_rowland-dotties-harvard-dot.s-edu> wrote:

RobJ wrote...

This is a weird situation.
Here's the history of how it got to this point.

All I can say is, sheesh!
Click to expand...
Heck, Win, a 3v p-p square wave at 600 MHz is just getting
interesting!

John
 
John Larkin wrote...
Winfield Hill wrote:

RobJ wrote...

This is a weird situation.
Here's the history of how it got to this point.

All I can say is, sheesh!

Heck, Win, a 3v p-p square wave at 600 MHz is just
getting interesting!
Click to expand...
For you perhaps, John, but not for RobJ.


--
Thanks,
- Win
 
John Larkin wrote:
On Fri, 31 Dec 2004 12:37:00 GMT, Fred Bloggs <nospam@nospam.com
wrote:



RobJ wrote:

There are no LVTTL/LVCMOS buffers out there that can handle anywhere near
528MHz.

That's what makes your requirement suspicious. You have mismanaged your
component configuration somewhere along the way. There are synthesizer
IC's that just produce 3.3V CMOS clock levels at 500MHz.



Never miss an opportunity for an insult, huh Fred?

I guess everybody who ever uses chips with different I/O level specs
is an idiot.

John
Click to expand...
It's not an insult, it is an observation that it is kind of dumb to set
a requirement that cannot be met by existing logic technology- somebody
was not thinking.
 
On Sat, 01 Jan 2005 13:29:17 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

John Larkin wrote:
On Fri, 31 Dec 2004 12:37:00 GMT, Fred Bloggs <nospam@nospam.com
wrote:



RobJ wrote:

There are no LVTTL/LVCMOS buffers out there that can handle anywhere near
528MHz.

That's what makes your requirement suspicious. You have mismanaged your
component configuration somewhere along the way. There are synthesizer
IC's that just produce 3.3V CMOS clock levels at 500MHz.



Never miss an opportunity for an insult, huh Fred?

I guess everybody who ever uses chips with different I/O level specs
is an idiot.

John


It's not an insult, it is an observation that it is kind of dumb to set
a requirement that cannot be met by existing logic technology- somebody
was not thinking.
Click to expand...

Well, "You have mismanaged your component configuration" sounded sorta
personal to me. Last design we did - just shipped the first units a
couple weeks ago - we had more level shifter chips on the board than
logic chips.

John
 
John Larkin <john@spamless.usa> wrote:

We're using the TI 74ALVC164245. Nice part... 16 bits in each
direction. Philips and IDT make it, too. Pericom may have an
equivalent, but their web site is so bad it's hard to tell.

Just when things were settling down, now we have to cope with lots of
different logic levels.
Click to expand...
Isn't that something to sort out first? For the (space constrained)
design I'm working on now, one of the first things I did was
eliminating the need for logic level converters. Makes live a whole
lot easier.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
 
Nico Coesel wrote:
Just when things were settling down, now we have to cope with lots of
different logic levels.

Isn't that something to sort out first? For the (space constrained)
design I'm working on now, one of the first things I did was
eliminating the need for logic level converters. Makes live a whole
lot easier.
Click to expand...
One of the reasons I rarely post questions to forums like this is that most
people are so damn judgmental. Instead of getting pointed responses to a
pointed question you get a bunch of "Why the hell did you do this?" or "Any
idiot knows you can't do that ...", and a ton of "I would have done this
instead ...". Then I have to fight the urge to waste time trying to explain
myself, when I know that no explanation will appease the know-it-alls.
Thanks to John Larkin for giving me good ideas without questioning why I
need to do what I'm doing.

Rob
 
On Sun, 2 Jan 2005 19:11:24 +0000, John Woodgate <jmw@jmwa.demon.contraspam.yuk>
wroth:

Besides, it's only human nature to ask, **sympathetically**, how you
came to paint yourself (or be painted by the management) into that
particular corner.
Click to expand...
After pulling Joe out of the river where he was doing a passable
imitation of a boat anchor, Bill asked, "How'd you come to fall in?"

Joe replied, "I didn't come to fall in, I came to go fishing!"

Jim
 
"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:jeobt052nk8rcnvvajop0uo1s446afrvhg@4ax.com...
Oh, scratch the LVDS receiver. I tried one and it gets weird above
about 300 MHz.

Opamp or MMIC, I guess.

John

I'm surprised you say that about LVDS - I've used FPGA LVDS
Click to expand...
outputs at 600MHz with no problems. Waveform was very clean,
except for about 100psec timing difference between positive and
negative transitions.

If LVDS is not an option for the OP, then the MMIC suggestion
you made would be the simplest way - keep the impedance level
at 50 ohms, it makes things a lot easier, use controlled impedance
lines and make sure it is terminated properly.

Regards
Ian
 
Ian wrote:
I'm surprised you say that about LVDS - I've used FPGA LVDS
outputs at 600MHz with no problems. Waveform was very clean,
except for about 100psec timing difference between positive and
negative transitions.
Click to expand...
Ian -

What FPGA family has that kind of LVDS output performance? Are you talking
about 600MHz clock or data outputs? Virtex-2 runs out of gas at around
400MHz for LVDS clock outputs (i.e., 800MHz data). I'd be really surprised
to hear that a Xilinx competitor can do 50% better than that.

Rob
 
RobJ wrote:

Ian wrote:

I'm surprised you say that about LVDS - I've used FPGA LVDS
outputs at 600MHz with no problems. Waveform was very clean,
except for about 100psec timing difference between positive and
negative transitions.



Ian -

What FPGA family has that kind of LVDS output performance? Are you talking
about 600MHz clock or data outputs? Virtex-2 runs out of gas at around
400MHz for LVDS clock outputs (i.e., 800MHz data). I'd be really surprised
to hear that a Xilinx competitor can do 50% better than that.
Click to expand...
Not Ian, nevertheless. There are very fast FPGA families,
such as the Altera Mercury, Altera Stratix, Altera StratixGX,
the last having 3.125 GBit transceivers.

http://www.altera.com/products/devices/stratixgx/sgx-index.jsp

The point is less in having the fast transceivers, than the
lower gate count.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
 
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