3 bit comparator...

[Dương Dương]

comparator3bit.vhd:library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity comparator3bit is
port (
p : in std_logic_vector(2 downto 0);
q : in std_logic_vector(2 downto 0);
p_le_q : out std_logic
);
end comparator3bit;

Architecture Behavior of comparator3bit is
begin
process (p, q)
begin
if p<q then p_le_q <= \'1\';
else p_le_q <= \'0\';
end if;
end process;
end Behavior;

comparator3bit_tb.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

entity comparator3bit_tb is
end comparator3bit_tb;

Architecture tb of comparator3bit_tb is
component comparator3bit_tb is
port ( p : in std_logic_vector(2 downto 0);
q : in std_logic_vector(2 downto 0);
p_le_q : out std_logic);
end component;
signal p,q : std_logic_vector(2 downto 0) := (others => \'0\');
signal p_le_q : std_logic;
signal i,j : integer;
begin
UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q => p_le_q);
process
begin
for i in 0 to 8 loop
p <= std_logic_vector(to_unsigned(i+2,3));
q <= std_logic_vector(to_unsigned(i,3));
end loop;
wait;
end process;
end;

When I run the simulation comparator3bit_tb and add the wave then the graph does not show p_le_q output. How to fix thanks