16 bit risc processor in VHDL

[kliga]

Hi,
I need to write behavioral VHDL code for RISC instruction set that
contains 8 instructions of each length is 16 bits.
there are 3 types of instructions for these 8 instructions
the 3 MSB of each instruction is for operation code.
i am using xilinx ISE.

this is sample of my code, i need your help
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu is
generic (
MAXWIDTH : integer := 16;
MAXDEPTH : integer := 12
);
end alu;

architecture Behavioral of alu is

-- CONSTANTS DECLARATION
constant ADD : std_logic_vector(2 downto 0) := "000";
constant ADDI : std_logic_vector(2 downto 0) := "001";
constant NND : std_logic_vector(2 downto 0) := "010";
constant LUI : std_logic_vector(2 downto 0) := "011";
constant SW : std_logic_vector(2 downto 0) := "100";
constant LW : std_logic_vector(2 downto 0) := "101";
constant BEQ : std_logic_vector(2 downto 0) := "110";
constant JALR : std_logic_vector(2 downto 0) := "111";

-- SIGNALS DECLARATION
signal opcode : std_logic_vector(MAXWIDTH-1 downto MAXWIDTH-3);
signal regA : std_logic_vector(MAXWIDTH-4 downto MAXWIDTH-6);
signal regB : std_logic_vector(MAXWIDTH-7 downto MAXWIDTH-5);
signal regC : std_logic_vector(MAXWIDTH-14 downto 0);
signal imm7: std_logic_vector(MAXWIDTH-10 downto 0);
signal imm10: std_logic_vector(MAXWIDTH-7 downto 0);

signal pc_reg : std_logic_vector(MAXWIDTH-1 downto 0);
signal pc_next : std_logic_vector(MAXWIDTH-1 downto 0);
signal ir_reg : std_logic_vector(MAXWIDTH-1 downto 0);
signal ir_next : std_logic_vector(MAXWIDTH-1 downto 0);
signal acc_reg : std_logic_vector(MAXWIDTH-1 downto 0);
signal acc_next : std_logic_vector(MAXWIDTH-1 downto 0);
begin
process
(
pc_reg, pc_next,
ir_reg, ir_next,
acc_reg, acc_next
)
variable opcode_v : std_logic_vector(2 downto 0);
begin
opcode <= ir_reg(MAXWIDTH-1 downto MAXWIDTH-3);
regA <= ir_reg(MAXWIDTH-4 downto MAXWIDTH-6);
regB <= ir_reg(MAXWIDTH-7 downto MAXWIDTH-5);
regC <= ir_reg(MAXWIDTH-14 downto 0);
imm7 <= ir_reg(MAXWIDTH-10 downto 0);
imm10 <= ir_reg(MAXWIDTH-7 downto 0);

opcode_v := opcode;
case (opcode_v) is
when ADD =>
regA <= regB + regC;



when NND =>
regA <= regB nand regC;

when others =>
pc_next <= pc_reg;
end case;
end process;

end Behavioral

 

[Rob Gaddi]

On Mon, 30 Nov 2015 11:17:51 -0800, kliga wrote:

Hi,
I need to write behavioral VHDL code for RISC instruction set that
contains 8 instructions of each length is 16 bits.
there are 3 types of instructions for these 8 instructions the 3 MSB of
each instruction is for operation code.
i am using xilinx ISE.

this is sample of my code, i need your help library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

If you're using numeric_std (which you should be) then you can't also use
std_logic_arith and std_logic_unsigned (which have been the wrong answer
for over 20 years now.)

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.