Kirstie Wong
Guest
Thu Mar 18, 2004 12:46 am
Hello, guys, i am implementing a Finite State Machine using VHDL, and
trying to get it synthesis, but i came up with the error with
=========================================================================
* Low Level Synthesis
*
=========================================================================
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<2>1> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<3>1> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<0>1> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<1>1> not replaced by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed
from the XST
what is the problem? and how can i solve it, it is very urgent, i am
only a beginner, please help~ =(
it seems that signal is stuck at ground in the schmetics from a MUX,,
here is some of my code that i think the problem i had, the fsm, is 3
process.
process1 (current_state, inputs........)
begin
case current_state is
when state0 =>
next_state <= state1; -- default assignment to avert latch
output1 <= '0';
outpput2 <= '1';
if ... else... stuff;;
end case;
end process;
process(CLOCK, RESET, over)
variable c_state : std_logic_vector(3 downto 0);
begin
--current_state <= current_state;
if (RESET = '1') then
next_state <= "0000";
elsif CLOCK'EVENT and CLOCK='1' then
if (over = '1') then
current_state <= next_state; --- here might be the problem that
produce the XST
5
else
current_state <= current_state;
end if;
end if;
end process;
process(current_state)
begin
PRESENT_STATE <= current_state;
end process;
end Behavioral;
Eyck Jentzsch
Guest
Thu Mar 18, 2004 6:22 am
Kirstie Wong wrote:
Quote:
Hello, guys, i am implementing a Finite State Machine using VHDL, and
trying to get it synthesis, but i came up with the error with
=========================================================================
* Low Level Synthesis
*
=========================================================================
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<2>1> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<3>1> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<0>1> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
signal <next_state<1>1> not replaced by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed
from the XST
what is the problem? and how can i solve it, it is very urgent, i am
only a beginner, please help~ =(
it seems that signal is stuck at ground in the schmetics from a MUX,,
here is some of my code that i think the problem i had, the fsm, is 3
process.
process1 (current_state, inputs........)
begin
case current_state is
when state0 =
next_state <= state1; -- default assignment to avert latch
output1 <= '0';
outpput2 <= '1';
if ... else... stuff;;
end case;
end process;
process(CLOCK, RESET, over)
variable c_state : std_logic_vector(3 downto 0);
begin
--current_state <= current_state;
if (RESET = '1') then
next_state <= "0000";
^^^^^^^^^^
I think you want to assign current_state, but by doing this you have a
driver for next_state in this process and in the previous one -> multidriven
Quote:
elsif CLOCK'EVENT and CLOCK='1' then
if (over = '1') then
current_state <= next_state; --- here might be the problem that
produce the XST
5
else
current_state <= current_state;
end if;
end if;
end process;
process(current_state)
begin
PRESENT_STATE <= current_state;
end process;
end Behavioral;
HTH
-Eyck
