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Xilinx Virtex4 Outputs for Camera Link

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Will Dean
Guest

Tue Oct 31, 2006 12:57 am   



"Brad Smallridge" <bradsmallridge_at_dslextreme.com> wrote in message
news:12kcsm5kh166g4a_at_corp.supernews.com...
Quote:

Pin count and input/output flexibility.

Pin-count is a good one - I hadn't thought of that. Does the Virtex design
track nicely to the 3M connectors?

Cheers,

Will

Rob
Guest

Tue Oct 31, 2006 3:14 am   



"Will Dean" <will_at_nospam.demon.co.uk> wrote in message
news:4546910e$0$631$bed64819_at_news.gradwell.net...
Quote:
"Rob" <robnstef_at_frontiernet.net> wrote in message
news:iwU0h.4200$Ka1.3743_at_news01.roc.ny...

I know you addressed this to Brad, but my answer would be all of the
above. I would counter your question with: if your design necessiates an
FPGA, and that FPGA is capabable of performing the deserialization, why
would you use the National chips?

Because it's easier. Which means that I can do something else, which
perhaps hasn't been done by someone else already...

Setting up the deserilizer within an FPGA, if you can use the mfg's module
(which you almost always can when it comes to cameral/channel link), takes
about 10 minutes--would you consider that easy? And if by chance you have
to build your own, and you understand the hardware, it doesn't take that
much longer. And in the end you have the tool in your box you can pull out
for the next job (reuse = no time).

Quote:

Sure, if you have to build your own, it can get tricky with setup/hold
times, jitter, skew, and clock phasing--but what's life w/o challenges?

Hmm. There's a hint of 'when did you stop beating your wife?' to that.
I do have a large quantity of white muscle t-shirts with food stains on

them!!

Quote:
Maybe I can parry by saying that I see the real engineering challenge as
to find the best way to do things, which doesn't necessarly mean
'gratuitously difficult'. Though I'll concede I do like to go for at
least a little bit of gratuitous difficulty on every new project.

The real benefit, at least in my world (image processing), is that I always
have an FPGA on the board which can do the interface; and my company is
always looking to cut board costs since they sell 10's and sometimes 100's
of thousands of units.

Quote:

If I built my own cameralink, and the camera mysteriously went out of sync
by one pixel every three weeks, I'd really regret it!

I believe statistically speaking it is almost impossible for an FPGA to
mysteriously go out of sync--there's always a logical reason. I work with a
group that tests these ports by running massive amounts of continuous data
through these interfaces--they all end up being solid. I have never run
into a mysterious missing pixel.

Furthermore, with the FPGA you can automatically adjust for skew in the
system. The National chips can't do this. And Brad does bring up another
great point about pin count.

Take care,
Rob


Quote:

Will



Gabor
Guest

Tue Oct 31, 2006 3:54 pm   



Brad Smallridge wrote:
[snip]
Quote:

Another vote for National Chips if the highest frequency at SDR is 57MHz.
The Camera Link standard should go to 80MHz.


Actually 85 MHz. x 7 = 595 Mb/s per link pair.

I've used the National chips at this frequency for some time now and
have
not found that I need to adjust skew, however we generally use fairly
expensive cabling to keep the pair-to-pair skew low. I would think the
pin count is the only good reason not to use the National chips. Also
make sure you have adequate ESD protection. I generally don't like
running external cables directly into expensive ball-grid arrays
(doubly
expensive to repair).

Just my 2 cents,
Gabor


Guest

Wed Mar 22, 2017 1:11 pm   



On Tuesday, October 31, 2006 at 5:27:42 AM UTC+5:30, Will Dean wrote:
Quote:
"Brad Smallridge" <bradsmallridge_at_dslextreme.com> wrote in message
news:12kcsm5kh166g4a_at_corp.supernews.com...

Pin count and input/output flexibility.

Pin-count is a good one - I hadn't thought of that. Does the Virtex design
track nicely to the 3M connectors?

Cheers,

Will


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