Chris Maryan
Guest
Thu Feb 25, 2010 12:21 am
Intuitively, the iodelay found in Xilinx parts should be just a tapped
delay line. But the need for a reference clock at a precise frequency
indicates otherwise. Does anyone have any insight into how these are
implemented?
I'm not looking for an exact answer, but any reasonable explanation
would be appreciated. The only idea I had is that it's a chain of FFs
driven on a very fast clock (ref clk multiplied up to give 75ns taps
~13GHz) which seems very improbable).
Any thoughts?
Thanks,
Chris
John McCaskill
Guest
Thu Feb 25, 2010 12:41 am
On Feb 24, 4:21 pm, Chris Maryan <kmar...@gmail.com> wrote:
Quote:
Intuitively, the iodelay found in Xilinx parts should be just a tapped
delay line.
Yes, that is what it is.
Quote:
But the need for a reference clock at a precise frequency
indicates otherwise. Does anyone have any insight into how these are
implemented?
The reference clock is used to calibrate the tapped delay line so that
it has a consistent delay that is resistant to changes in process,
voltage and temperature.
Quote:
I'm not looking for an exact answer, but any reasonable explanation
would be appreciated. The only idea I had is that it's a chain of FFs
driven on a very fast clock (ref clk multiplied up to give 75ns taps
~13GHz) which seems very improbable).
Any thoughts?
Thanks,
Chris
Regards,
John McCaskill
www.FasterTechnology.com
