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colin
Guest

Thu Oct 06, 2016 10:40 am   



Guys

I have two FPGAs with 4 MGTs connected between them using Aurora. The firmware guy has insisted (and I've taken a quick look myself) that we cannot define the link order. This means that I have to layout the PCB with the MGTs crossing over each other.

Really?

I can't easily ask Xilinx directly because it is the firmware guys responsibility hence my post here.
Does anyone here know whether this is definitely the case or not?

Sorry to use google to post this. I am certain that making a technical request to an admin dept run by HP in India to allow me proper usenet access will not succeed.

Colin

colin
Guest

Thu Oct 06, 2016 4:36 pm   



Allan

We tried a build by just changing the pinout and it fails. The Aurora wizard has a setting where you tell it the first MGT you want to use and then it uses the consecutive MGTs as required. It "helps" by then locking down where some of the logic is placed within the FPGA and so meeting timing becomes impossible if you change MGT locations.

I had hoped our firmware guy had given up on finding a different Aurora wizard setting because he is busy and it is not a problem he needs to solve.

cheers,

Colin

Allan Herriman
Guest

Thu Oct 06, 2016 8:19 pm   



On Thu, 06 Oct 2016 01:40:32 -0700, colin wrote:

Quote:
Guys

I have two FPGAs with 4 MGTs connected between them using Aurora. The
firmware guy has insisted (and I've taken a quick look myself) that we
cannot define the link order. This means that I have to layout the PCB
with the MGTs crossing over each other.

Really?

I can't easily ask Xilinx directly because it is the firmware guys
responsibility hence my post here.
Does anyone here know whether this is definitely the case or not?

Sorry to use google to post this. I am certain that making a technical
request to an admin dept run by HP in India to allow me proper usenet
access will not succeed.


I have had similar issues with different interfaces that used multiple
transceiver channels bonded. In my case, I could specify any order I
wanted just by changing the pin numbers for the various transceivers in
the constraints file.
I understand that the internal connections between the transceivers and
the core go via regular FPGA fabric, and as such you should be able to
swap the transceivers around (unless operating at high clock rates, which
might make it difficult to route to speed if you choose some wildly sub-
optimal ordering).

It ought to be pretty quick to test that in whatever tool you're using -
just change the pinout and see if it builds.


I guess you also have DC blocking caps on the transceiver signals. This
implies that you'll have vias on the traces (to get them to an outer
layer), which makes it pretty easy to swap the pairs around on the PCB if
you can't get the FPGA tools to cooperate.

Allan

Allan Herriman
Guest

Fri Oct 07, 2016 4:04 am   



On Thu, 06 Oct 2016 07:36:58 -0700, colin wrote:

Quote:
Allan

We tried a build by just changing the pinout and it fails. The Aurora
wizard has a setting where you tell it the first MGT you want to use and
then it uses the consecutive MGTs as required. It "helps" by then
locking down where some of the logic is placed within the FPGA and so
meeting timing becomes impossible if you change MGT locations.

I had hoped our firmware guy had given up on finding a different Aurora
wizard setting because he is busy and it is not a problem he needs to
solve.


I suggest asking your question again in this forum:
https://forums.xilinx.com/t5/Networking-and-Connectivity/bd-p/CONN

BTW, An earlier thread in that forum may have the answers you want:
https://forums.xilinx.com/t5/Networking-and-Connectivity/Aurora-8B-10B-in-XC7K325-GTX-pin-assignments/m-p/713409

Regards,
Allan

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