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why modelsim function simulation have glitch happen?

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Sand Glass
Guest

Fri Jul 06, 2018 11:45 am   



ENV:modelsim 10.2c 32bit; debussy5.4; win7 x64 OS.
In the picture, blk_done_p have a glitch in red circle. I
Does the dangerous? If does, how to avoid?



`ifndef DLY
`define DLY 0
`endif
module test_glitch (
//Inputs
clk_bus, brst_n,

//Outputs
tile_done_p);

input clk_bus;//clock
input brst_n;//reset

output tile_done_p;

reg [1:0] cnt_h;
reg [3:0] cnt_w;
wire blk_done_p;
wire blky_row_done_p;
wire [1:0] enable;
wire frame_init_p;

assign frame_init_p = 1'b0;
assign enable[1:0] = 2'b11;
always @(posedge clk_bus or negedge brst_n) begin
if (!brst_n) begin
cnt_w <= #`DLY 4'd0;
end
else if (frame_init_p) begin
cnt_w <= #`DLY 4'd0;
end
else if(blky_row_done_p)begin
cnt_w <= #`DLY 4'd0;
end
else if(enable[0])begin
cnt_w <= #`DLY cnt_w + 1'b1;
end
end
always @(posedge clk_bus or negedge brst_n) begin
if (!brst_n) begin
cnt_h <= #`DLY 2'd0;
end
else if (frame_init_p) begin
cnt_h <= #`DLY 2'd0;
end
else if(blk_done_p)begin
cnt_h <= #`DLY 2'd0;
end
else if(blky_row_done_p)begin
cnt_h <= #`DLY cnt_h + 1'b1;
end
end
assign blky_row_done_p = enable[0] & (cnt_w == 15);
assign blk_done_p = blky_row_done_p & (cnt_h == 2'd3);
endmodule

////This is the sim.do script; flist.f have the test_glitch.v file.
//vlib work
//vlog -timescale "1ns/1ps" -f flist.f
//vsim work.tb_top
//run -all
//quit

Sand Glass
Guest

Fri Jul 06, 2018 11:45 am   



I don't know how to upload the image. So put the image in my Chinese web:
http://bbs.eetop.cn/viewthread.php?tid=764754&page=1&extra=#pid9712789

Gabor
Guest

Fri Jul 06, 2018 11:45 pm   



On Friday, 7/6/2018 5:58 AM, Sand Glass wrote:
Quote:
ENV:modelsim 10.2c 32bit; debussy5.4; win7 x64 OS.
In the picture, blk_done_p have a glitch in red circle. I
Does the dangerous? If does, how to avoid?



`ifndef DLY
`define DLY 0
`endif
module test_glitch (
//Inputs
clk_bus, brst_n,

//Outputs
tile_done_p);

input clk_bus;//clock
input brst_n;//reset

output tile_done_p;

reg [1:0] cnt_h;
reg [3:0] cnt_w;
wire blk_done_p;
wire blky_row_done_p;
wire [1:0] enable;
wire frame_init_p;

assign frame_init_p = 1'b0;
assign enable[1:0] = 2'b11;
always @(posedge clk_bus or negedge brst_n) begin
if (!brst_n) begin
cnt_w <= #`DLY 4'd0;
end
else if (frame_init_p) begin
cnt_w <= #`DLY 4'd0;
end
else if(blky_row_done_p)begin
cnt_w <= #`DLY 4'd0;
end
else if(enable[0])begin
cnt_w <= #`DLY cnt_w + 1'b1;
end
end
always @(posedge clk_bus or negedge brst_n) begin
if (!brst_n) begin
cnt_h <= #`DLY 2'd0;
end
else if (frame_init_p) begin
cnt_h <= #`DLY 2'd0;
end
else if(blk_done_p)begin
cnt_h <= #`DLY 2'd0;
end
else if(blky_row_done_p)begin
cnt_h <= #`DLY cnt_h + 1'b1;
end
end
assign blky_row_done_p = enable[0] & (cnt_w == 15);
assign blk_done_p = blky_row_done_p & (cnt_h == 2'd3);
endmodule

////This is the sim.do script; flist.f have the test_glitch.v file.
//vlib work
//vlog -timescale "1ns/1ps" -f flist.f
//vsim work.tb_top
//run -all
//quit


The glitch is real because blk_done_p is decoding multiple outputs
of your state logic. It's dangerous if you're using blk_done_p as
an asynchronous signal, for example as a reset, or a latch enable,
or a clock. It's not dangerous if you're only using blk_done_p as
a synchronous signal, i.e. going to the D of another flip-flop on
the same clock. If you need to use blk_done_p asynchronously, you
should use a synchronous process to create it perhaps like:

(within the clocked process)

blk_done_p <= (cnt_h == 2'd3) && (cnt_w == 14);

--
Gabor

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