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Why differences between Merly-type and Moore-type clock-gate

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Weng Tianxiang
Guest

Fri Aug 09, 2019 10:45 pm   



Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?

I need help to understand a puzzle:

Merly-type state machine generates outputs which depend on inputs to the state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine.
Am I right if I treat a Merly-type state machine as a Moore-type state machine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs?
If I am right, why the paper "Automatic synthesis of lower power gated-clock finite state machine"
https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss6Jun96pg630.pdf
says (p.632, 2nd column, last section) "The knowledge of the state and the input is not sufficient to individuate the conditions when the clock can be stopped."

Thank you.

Weng

Rick C
Guest

Fri Aug 09, 2019 11:45 pm   



On Friday, August 9, 2019 at 4:53:12 PM UTC-4, Weng Tianxiang wrote:
Quote:
Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?

I need help to understand a puzzle:

Merly-type state machine generates outputs which depend on inputs to the state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine.
Am I right if I treat a Merly-type state machine as a Moore-type state machine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs?
If I am right, why the paper "Automatic synthesis of lower power gated-clock finite state machine"
https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss6Jun96pg630.pdf
says (p.632, 2nd column, last section) "The knowledge of the state and the input is not sufficient to individuate the conditions when the clock can be stopped."


I believe any Moore type FSM can be converted to any Mealy type FSM and vice versa. That would imply that the two types of FSM should be equivalent in this consideration.

However, your question actually has nothing to do with the distinction of the two types of FSM.

I would also point out the definition of the Mealy type FSM is often not well specified. While they define it as having outputs dependent on the inputs as well as the state, I find they are usually implemented with registered outputs. This effectively makes them Moore type FSM even if those outputs are not provided as inputs to the FSM logic.

The paper PDF file does not allow copying of text, so I won't go into this much, but this paper has fundamental errors I believe. For one, they mention there are "conditions such that the outputs and next state do not change". Then they go on to say stopping the clock will save power in the combinational logic because the outputs of registers are prevented from changing. What registers would those be??? If the outputs and registers are not changing, what would be changing that would make the combinational logic consume power???

Finally, I would submit it is very easy to determine if a FF should be clocked or not. Simply compare the D input to the Q output. If they are the same, gate the clock. If they are different enable the clock. BTW, this effectively turns the D FF into a toggle FF.

Isn't this whole thing a bit of a DUH! Not very patentable since it is obvious to anyone skilled in the field.

BTW, how is the wave pipelining thing going?

--

Rick C.

- Get 1,000 miles of free Supercharging
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Weng Tianxiang
Guest

Sat Aug 10, 2019 1:45 am   



On Friday, August 9, 2019 at 3:32:29 PM UTC-7, Rick C wrote:
Quote:
On Friday, August 9, 2019 at 4:53:12 PM UTC-4, Weng Tianxiang wrote:
Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?

I need help to understand a puzzle:

Merly-type state machine generates outputs which depend on inputs to the state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine.
Am I right if I treat a Merly-type state machine as a Moore-type state machine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs?
If I am right, why the paper "Automatic synthesis of lower power gated-clock finite state machine"
https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss6Jun96pg630.pdf
says (p.632, 2nd column, last section) "The knowledge of the state and the input is not sufficient to individuate the conditions when the clock can be stopped."

I believe any Moore type FSM can be converted to any Mealy type FSM and vice versa. That would imply that the two types of FSM should be equivalent in this consideration.

However, your question actually has nothing to do with the distinction of the two types of FSM.

I would also point out the definition of the Mealy type FSM is often not well specified. While they define it as having outputs dependent on the inputs as well as the state, I find they are usually implemented with registered outputs. This effectively makes them Moore type FSM even if those outputs are not provided as inputs to the FSM logic.

The paper PDF file does not allow copying of text, so I won't go into this much, but this paper has fundamental errors I believe. For one, they mention there are "conditions such that the outputs and next state do not change". Then they go on to say stopping the clock will save power in the combinational logic because the outputs of registers are prevented from changing. What registers would those be??? If the outputs and registers are not changing, what would be changing that would make the combinational logic consume power???

Finally, I would submit it is very easy to determine if a FF should be clocked or not. Simply compare the D input to the Q output. If they are the same, gate the clock. If they are different enable the clock. BTW, this effectively turns the D FF into a toggle FF.

Isn't this whole thing a bit of a DUH! Not very patentable since it is obvious to anyone skilled in the field.

BTW, how is the wave pipelining thing going?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209


Hi Rick,

Thank you very much! I fully agree with your opinion, especially your following opinion:

>Simply compare the D input to the Q output. If they are the same, gate the clock. If they are different enable the clock. BTW, this effectively turns the D FF into a toggle FF.

Weng

KJ
Guest

Sat Aug 10, 2019 4:45 am   



On Friday, August 9, 2019 at 4:53:12 PM UTC-4, Weng Tianxiang wrote:
Quote:
Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?
Refer to my post on comp.lang.vhdl at https://groups.google.com/forum/#!topic/comp.lang.vhdl/E4YvtRSYTdU where I explain the error of the writer's ways (Hint: The writers didn't really have a Mealy state machine in the first place...at least not in Figure 1)


Kevin Jennings

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