Why Can't I get This FET To Oscillate

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10 uF,
and the three resistors to common are 150k each. The FET is a MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


--
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Just when you thought you had all this figured out, the gov't
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@@t_at_h_at_e@@a_at_f_at_f_at_l_at_u_at_e_at_n_at_t@@m_at_e_at_e_at_t@@t_at_h_at_e@@E_at_f_at_f_at_l_at_u_at_e_at_n_at_t@@

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10 uF,
and the three resistors to common are 150k each. The FET is a MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.

Hi,
try increasing Rd. The gain of the cct should be gmRd so you need to
check
the typical figure for gm ( 2000 to 7500uS for a 102) and then
determine the
correct minimum Rd. Try using a pot.
if gm =2000 then Rd = 14k5
if gm = 7500 then Rd = 3k9

Cheers
Greg

"Watson A.Name - "Watt Sun, the Dark Remover"" <NOSPAM_at_dslextreme.com
wrote
in message news:10tcm7tjjrb5k93_at_corp.supernews.com...
I built up a FET version of the phase shift oscillator on the right
of

http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain
load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10
uF,
and the three resistors to common are 150k each. The FET is a
MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the
DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in
the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


--
@@F_at_r_at_o_at_m@@O_at_r_at_a_at_n_at_g_at_e@@C_at_o_at_u_at_n_at_t_at_y@,@@C_at_a_at_l@,@@w_at_h_at_e_at_r_at_e@@
###Got a Question about ELECTRONICS? Check HERE First:###
http://users.pandora.be/educypedia/electronics/databank.htm
My email address is whitelisted. *All* email sent to it
goes directly to the trash unless you add NOSPAM in the
Subject: line with other stuff. alondra101 <at> hotmail.com
Don't be ripped off by the big book dealers. Go to the URL
that will give you a choice and save you money(up to half).
http://www.everybookstore.com You'll be glad you did!
Just when you thought you had all this figured out, the gov't
changed it: http://physics.nist.gov/cuu/Units/binary.html
@@t_at_h_at_e@@a_at_f_at_f_at_l_at_u_at_e_at_n_at_t@@m_at_e_at_e_at_t@@t_at_h_at_e@@E_at_f_at_f_at_l_at_u_at_e_at_n_at_t@@

On Sat, 1 Jan 2005 00:04:06 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\"" <NOSPAM_at_dslextreme.com> wrote:

I built up a FET version of the phase shift oscillator on the right
of

http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain
load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10
uF,
and the three resistors to common are 150k each. The FET is a
MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the
DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in
the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


In addition to the need for gain (and jfets have low gain) the
"lead"-type phase shift network needs to see a low impedance at its
output. A bipolar base provides this low impedance, a fet doesn't. A
lag-type phase shifter is more appropriate for a fet.

But phase-shift oscillators tend to be rotten anyhow.

Hey, this guy has a few really terrible circuits on his web page!

Watson A.Name - "Watt Sun, the Dark Remover" wrote:

I built up a FET version of the phase shift oscillator on the right
of

http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain
load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10
uF,
and the three resistors to common are 150k each. The FET is a
MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the
DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in
the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


--

the source should be on the resistor side and the drain to the 9volts.
i don't know if that will fix it, also did you make sure you used
a jFet and not a MOSFET?

Thanks. The first JFET I used needed a 1.5k for the source resistor. I
increased the drain load from 3.9k to 10k, to get more gain, but of
course that meant a higher source resistor for more neg V on the gate.
So instead I put a 1N4148 in series with the resistor to give a .6 or so
volt dtop. That helped bring the drain voltage up to closer to half the
9V supply voltage. But it still wouldn't osc, just a damped sine wave.
So I swapped the JFET, and that got it to be a bit better, but still a
damped sine wave. I decided to put another 1000 uF across the source
bypass cap, total 2000, and it helped a bit. So I kept putting more of
them across, and the damped wave kept getting longer. I'm up to 5400
uF, and it will 'ring' for more than a minute but it's still a damped
sine wave. I'm gonna try a higher value drain load, as you suggest.
But I still have to deal with rebiasing it with a higher source
resistor. I used a pot, but I guess it wasn't high enough value. I'll
tinker with it some more after awhile.

One thing that's always bothered me about JFETs is that there is so much
variance in the gm and Idss from part to part. Now that I have a
bagful, I'm not so concerned with having to swap them to find the 'right
one'. Before, I was lucky to find two of them at Rat Shaft, and with my
luck, they'd both be the same. And I wasn't about to go all over town
to buy more and have to spend tens of dollars to do so.

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10 uF,
and the three resistors to common are 150k each. The FET is a MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


--
@@F_at_r_at_o_at_m@@O_at_r_at_a_at_n_at_g_at_e@@C_at_o_at_u_at_n_at_t_at_y@,@@C_at_a_at_l@,@@w_at_h_at_e_at_r_at_e@@
###Got a Question about ELECTRONICS? Check HERE First:###
http://users.pandora.be/educypedia/electronics/databank.htm
My email address is whitelisted. *All* email sent to it
goes directly to the trash unless you add NOSPAM in the
Subject: line with other stuff. alondra101 <at> hotmail.com
Don't be ripped off by the big book dealers. Go to the URL
that will give you a choice and save you money(up to half).
http://www.everybookstore.com You'll be glad you did!
Just when you thought you had all this figured out, the gov't
changed it: http://physics.nist.gov/cuu/Units/binary.html
@@t_at_h_at_e@@a_at_f_at_f_at_l_at_u_at_e_at_n_at_t@@m_at_e_at_e_at_t@@t_at_h_at_e@@E_at_f_at_f_at_l_at_u_at_e_at_n_at_t@@


the source should be on the resistor side and the drain to the 9volts.

On Sat, 01 Jan 2005 00:04:06 -0800, Watson A.Name - "Watt Sun, the
Dark
Remover" wrote:

I built up a FET version of the phase shift oscillator on the right
of

http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

Do you mean this one?

http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#phase.gif

you link puts me at "Triangle and Squarewave Generator".

If you mean the "Low Frequency Sinewave Generators",

I used a 1.5k source resistor bypassed by a 1000 uF cap.

Well, that'll kinda degenerate your source follower output.

The drain load
resistor is 3.9k, and the supply voltage is 9VDC.

This confuses me, because the circuit I see has no drain load
resistor,
it's merely a source follower buffer. The 2N3906 is the gain element.

Or are you talking about a completely different circuit?

Thanks,
Rich

"Watson A.Name - \"Watt Sun, the Dark Remover\"" wrote:


Thanks. The first JFET I used needed a 1.5k for the source
resistor. I
increased the drain load from 3.9k to 10k, to get more gain, but of
course that meant a higher source resistor for more neg V on the
gate.
So instead I put a 1N4148 in series with the resistor to give a .6
or so
volt dtop. That helped bring the drain voltage up to closer to half
the
9V supply voltage. But it still wouldn't osc, just a damped sine
wave.
So I swapped the JFET, and that got it to be a bit better, but still
a
damped sine wave. I decided to put another 1000 uF across the
source
bypass cap, total 2000, and it helped a bit. So I kept putting more
of
them across, and the damped wave kept getting longer. I'm up to
5400
uF, and it will 'ring' for more than a minute but it's still a
damped
sine wave. I'm gonna try a higher value drain load, as you suggest.
But I still have to deal with rebiasing it with a higher source
resistor. I used a pot, but I guess it wasn't high enough value.
I'll
tinker with it some more after awhile.

One thing that's always bothered me about JFETs is that there is so
much
variance in the gm and Idss from part to part. Now that I have a
bagful, I'm not so concerned with having to swap them to find the
'right
one'. Before, I was lucky to find two of them at Rat Shaft, and
with my
luck, they'd both be the same. And I wasn't about to go all over
town
to buy more and have to spend tens of dollars to do so.

I would be tempted to put a pair of NPN emitter followers on the
drain, one for the output and one to drive the capacitive line.
--
John Popelish

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

"John Popelish" <jpopelish_at_rica.net> wrote in message
news:41D72C55.8860A749_at_rica.net...
"Watson A.Name - \"Watt Sun, the Dark Remover\"" wrote:


Thanks. The first JFET I used needed a 1.5k for the source
resistor. I
increased the drain load from 3.9k to 10k, to get more gain, but of
course that meant a higher source resistor for more neg V on the
gate.
So instead I put a 1N4148 in series with the resistor to give a .6
or so
volt dtop. That helped bring the drain voltage up to closer to half
the
9V supply voltage. But it still wouldn't osc, just a damped sine
wave.
So I swapped the JFET, and that got it to be a bit better, but still
a
damped sine wave. I decided to put another 1000 uF across the
source
bypass cap, total 2000, and it helped a bit. So I kept putting more
of
them across, and the damped wave kept getting longer. I'm up to
5400
uF, and it will 'ring' for more than a minute but it's still a
damped
sine wave. I'm gonna try a higher value drain load, as you suggest.
But I still have to deal with rebiasing it with a higher source
resistor. I used a pot, but I guess it wasn't high enough value.
I'll
tinker with it some more after awhile.

One thing that's always bothered me about JFETs is that there is so
much
variance in the gm and Idss from part to part. Now that I have a
bagful, I'm not so concerned with having to swap them to find the
'right
one'. Before, I was lucky to find two of them at Rat Shaft, and
with my
luck, they'd both be the same. And I wasn't about to go all over
town
to buy more and have to spend tens of dollars to do so.

I would be tempted to put a pair of NPN emitter followers on the
drain, one for the output and one to drive the capacitive line.
--
John Popelish

I thing that might be a good idea. But I have a couple theories or
ruminations.

This is a 'lead' network. Three CR sections with the last one directly
driving the gate, which is (nearly) infinite input impedance. Each
section contributes 60 degrees phase shift, but say each one was
contributing 45 degrees. Then the reactance of the caps would equal the
resistance of the resistors, which is 150k. So 60 degrees isn't that
much diff, the tangent of 60 is 1.732, but I forget which way, so either
the cap reactance is 150k * 1.732 or 150k / 1.732 (the former makes more
sense). We're talking about an impedance that's considerably above the
drain resistor (which is 16k for now), and much lower than the input
impedance.

"Watson A.Name - "Watt Sun, the Dark Remover"" <NOSPAM_at_dslextreme.com
wrote
in message news:10tcm7tjjrb5k93_at_corp.supernews.com...
I built up a FET version of the phase shift oscillator on the right
of

http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

Couldn't resist it!. Tried Wien arrangements, then gyrated LCs but the
single FETs and transistors just kept running out of gain.
Don't know whether that FET was the main interest, or just that a L.F.
Sine
was wanted but the same circuit using an NPN seems to useably work.
regards
john


+9V
|
.-.
| |
27k| |
'-'
|
.------------------------------------o----o 0.1Hz
| ___ ___ | 4Vpp
| .--|___|--o-|___|-o
| | 1M | 1M |
--- | | |
---10u | --- |
| | 10u--- |
| | | |
| || || | GND |/
o----||---o--||----o---------------| Jelly Bean
| || | || |
| 10u | 10u |
| | o----.
| | | |
.-. .-. .-. |
| |82k | |100k | | |
| | | | 27k| | ---
'-' '-' '-' ---1000u
| | | |
=== === === ===
GND GND GND GND

(created by AACircuit v1.28 beta 10/06/04 www.tech-chat.de)

"Watson A.Name - "Watt Sun, the Dark Remover"" <NOSPAM_at_dslextreme.com
wrote
in message news:10ters8r47ckv70_at_corp.supernews.com...

"John Popelish" <jpopelish_at_rica.net> wrote in message
news:41D72C55.8860A749_at_rica.net...
"Watson A.Name - \"Watt Sun, the Dark Remover\"" wrote:


Thanks. The first JFET I used needed a 1.5k for the source
resistor. I
increased the drain load from 3.9k to 10k, to get more gain, but
of
course that meant a higher source resistor for more neg V on the
gate.
So instead I put a 1N4148 in series with the resistor to give a
..6
or so
volt dtop. That helped bring the drain voltage up to closer to
half
the
9V supply voltage. But it still wouldn't osc, just a damped sine
wave.
So I swapped the JFET, and that got it to be a bit better, but
still
a
damped sine wave. I decided to put another 1000 uF across the
source
bypass cap, total 2000, and it helped a bit. So I kept putting
more
of
them across, and the damped wave kept getting longer. I'm up to
5400
uF, and it will 'ring' for more than a minute but it's still a
damped
sine wave. I'm gonna try a higher value drain load, as you
suggest.
But I still have to deal with rebiasing it with a higher source
resistor. I used a pot, but I guess it wasn't high enough value.
I'll
tinker with it some more after awhile.

One thing that's always bothered me about JFETs is that there is
so
much
variance in the gm and Idss from part to part. Now that I have a
bagful, I'm not so concerned with having to swap them to find the
'right
one'. Before, I was lucky to find two of them at Rat Shaft, and
with my
luck, they'd both be the same. And I wasn't about to go all
over
town
to buy more and have to spend tens of dollars to do so.

I would be tempted to put a pair of NPN emitter followers on the
drain, one for the output and one to drive the capacitive line.
--
John Popelish

I thing that might be a good idea. But I have a couple theories or
ruminations.

This is a 'lead' network. Three CR sections with the last one
directly
driving the gate, which is (nearly) infinite input impedance. Each
section contributes 60 degrees phase shift, but say each one was
contributing 45 degrees. Then the reactance of the caps would equal
the
resistance of the resistors, which is 150k. So 60 degrees isn't
that
much diff, the tangent of 60 is 1.732, but I forget which way, so
either
the cap reactance is 150k * 1.732 or 150k / 1.732 (the former makes
more
sense). We're talking about an impedance that's considerably above
the
drain resistor (which is 16k for now), and much lower than the input
impedance.

Bingo. Calculate the phase shift of the third section if it works into
an
infinite impedance (JFET input impedance.)

"BFoelsch" <BFoelsch_at_comcast.ditch.this.net> wrote in message
news:h4adnXm-OP3Xj0XcRVn-tw_at_giganews.com...

"Watson A.Name - "Watt Sun, the Dark Remover"" <NOSPAM_at_dslextreme.com
wrote
in message news:10ters8r47ckv70_at_corp.supernews.com...

"John Popelish" <jpopelish_at_rica.net> wrote in message
news:41D72C55.8860A749_at_rica.net...
"Watson A.Name - \"Watt Sun, the Dark Remover\"" wrote:


Thanks. The first JFET I used needed a 1.5k for the source
resistor. I
increased the drain load from 3.9k to 10k, to get more gain, but
of
course that meant a higher source resistor for more neg V on the
gate.
So instead I put a 1N4148 in series with the resistor to give a
.6
or so
volt dtop. That helped bring the drain voltage up to closer to
half
the
9V supply voltage. But it still wouldn't osc, just a damped sine
wave.
So I swapped the JFET, and that got it to be a bit better, but
still
a
damped sine wave. I decided to put another 1000 uF across the
source
bypass cap, total 2000, and it helped a bit. So I kept putting
more
of
them across, and the damped wave kept getting longer. I'm up to
5400
uF, and it will 'ring' for more than a minute but it's still a
damped
sine wave. I'm gonna try a higher value drain load, as you
suggest.
But I still have to deal with rebiasing it with a higher source
resistor. I used a pot, but I guess it wasn't high enough value.
I'll
tinker with it some more after awhile.

One thing that's always bothered me about JFETs is that there is
so
much
variance in the gm and Idss from part to part. Now that I have a
bagful, I'm not so concerned with having to swap them to find the
'right
one'. Before, I was lucky to find two of them at Rat Shaft, and
with my
luck, they'd both be the same. And I wasn't about to go all
over
town
to buy more and have to spend tens of dollars to do so.

I would be tempted to put a pair of NPN emitter followers on the
drain, one for the output and one to drive the capacitive line.
--
John Popelish

I thing that might be a good idea. But I have a couple theories or
ruminations.

This is a 'lead' network. Three CR sections with the last one
directly
driving the gate, which is (nearly) infinite input impedance. Each
section contributes 60 degrees phase shift, but say each one was
contributing 45 degrees. Then the reactance of the caps would equal
the
resistance of the resistors, which is 150k. So 60 degrees isn't
that
much diff, the tangent of 60 is 1.732, but I forget which way, so
either
the cap reactance is 150k * 1.732 or 150k / 1.732 (the former makes
more
sense). We're talking about an impedance that's considerably above
the
drain resistor (which is 16k for now), and much lower than the input
impedance.

Bingo. Calculate the phase shift of the third section if it works into
an
infinite impedance (JFET input impedance.)

Well, each CR has to be 60 degrees to give the 180 total needed.