Why Can't I get This FET To Oscillate

On Sat, 8 Jan 2005 09:45:14 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM_at_dslextreme.com> wrote:



But as I pointed out in another post, this also means that you
have
lots of feedback at
high frequencies. The MPF102 is specified as a VHF amplifier. You
could more easily have
parasitic oscillations at some high radio frequency that would
upset
the operation of the
circuit with the lead topology.

Well, with impedances of megohms and a load resistor of 33k, the
parasitic capacitances make a low pass filter

But you also have in series with every component, the parasitic
inductance of the leads,
especially with a bread board type setup. I can usually tell when
there are VHF
oscillations because of the "antenna" effect. You put your hand
within an inch of the
circuit and get major changes in behavior. I think you would have
noticed if this were
happening. Anyway, you're not using the lead form of the network now.

that makes it difficult to
oscillate at those freqs. With BJTs, the usual method is to put a 47
pF
from the collector to base,

Again, the leads of the 47 pF cap have inductance, especially when
breadboarding where
the leads are left long, and there is a frequency where the cap and
its leads are series
resonant. This can *cause* oscillations, rather than suppress them,
if the transistor has
a high enough cutoff frequency. I used to think it would be a good
idea to have a
transistor with a very high cutoff frequency to use for everything.
That way you would
never have to worry if the transistor was fast enough. So I tried
using a 2N3866 for
breadboarding; bad mistake. Almost everything you build with a 2N3866
will oscillate if
you use *breadboard* techniques.

or an even larger value across the collector
load resistor.

Higher
harmonics at the collector get fed back to the base where they are
cancelled.

I think it's been on long enough to stabilize and the oscs are
damped
out. BRB. Well, the oscs are almost damped out, and I measure
across
one of the 330ks about 1 to 2 mV, which is about .005 uA leakage.
That's less than .02V across the 4.3M bias resistor. But now that
it's
damped out and stable, I'll measure the DCV across the 4.3M. BRB.
Well, the meter is still jumping around zero, but as best as I can
tell
it's swinging from neg 10mV to pos 11 or 12mV, which seems to
agree
somewhat with the leakage estimate. Of course I didn't include
the
DMM's resistance, but I think it's 100M on the 200mV range.

I'm convinced that the leakage isn't a prob, and changing the cap
isn't
gonna help. What do you say?? Maybe I should try a 10uF
tantalum,
but
is that gonna be a help?

Here's a suggestion. Get rid of the components you have in the
source lead now. Make
a small stiff, adjustable bias supply by connecting 3 penlight
alkaline cell in series.
Put a 100 ohm (or thereabouts) trimpot across the 4.5 volt battery.
Connect the most
negative terminal of the battery to ground, and connect the source
of
the FET to the wiper
of the trimpot. You will have gotten rid of a big capacitor and
possible source of long
time constant behavior, and have an easily adjustable, low
impedance
bias supply.

I could just use the 9V supply and a resistor and zener to do that,
instead. Same diff and it saves batteries.

I have gotten the impression that your 9V supply is a "transistor
radio" type 9V
battery. I was thinking that the 3 penlight cells would have
substantially longer life
when providing the proposed low impedance bias supply.

Anyway, I think the variable bias supply and no capacitor would be
a good experiment to
try.

Thanks.

[snip]

On Sat, 8 Jan 2005 09:45:14 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM_at_dslextreme.com> wrote:



I made up a jig with a socket for the FETs. I used two 9V batts, one
for the drain supply and the other for the neg bias on the gate.
Below
are the values I got for the Vgs(off). The data sheet uses 15V on
the
drain, but I used only 9VDC, so it isn't exactly the same, but close.
It was really difficult to get the 100k neg V adjust pot to stay put
at
2 nA (which was 2 mV across a 1M rsistor). I measured a total of 26
MPF102s, some Moto's, some Signetics, some not marked with a logo.

MPF102 (26 total measured) Jan 7, 2005
Vgs(off) @ Vds=9V, Id=2nA (2mV across 1M)
(all voltages negative. Datasheet specs use Vds=15V)

3.56, 3.34, 1.90, 3.46, 2.44, 3.69, 3.97, 3.21, 3.58,
3.44, 2.20, 2.96, 2.39, 4.65, 3.47, 4.06, 3.28, 4.02,
3.76, 2.62, 1.92, 2.85, 3.05, 3.14, 3.55, 2.10**

**The 2.10V is the JFET I have been using for the oscillator.

As you can see, altho there was a somewhat wide variation, most of
them
were in the 2 to 4V range.

With Vgs(off) in this range, your FETs should have
transconductances much higher than
the 2000 minimum. I just can't understand the behavior you're getting
(oscillations dying
out). I may have to see if I can find an MPF102 of my own and
breadboard this thing.

I hope you can try the fixed source bias idea; I think we could get
some good info from
that.

On Sat, 8 Jan 2005 19:26:03 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\"" <NOSPAM_at_dslextreme.com> wrote:


Anyway, I think the variable bias supply and no capacitor would
be
a good experiment to
try.

Well, I still have to bypass the bias supply,

You bypassed it with 3200uF before; at .67Hz that's an impedance of
74 ohms. Why do a lot better than that now? If you put a 100 ohm
trimpot across your bias supply with the wiper connected to the source
as I proposed, you would have a maximum of 25 ohms source resistance
(with the trimpot set in the middle; less at any other setting)
without any capacitor, which I think would be a good thing; (the lack
of a capacitor, that is . Getting rid of the capacitor also
eliminates the complication of extra phase shift that John Jardine
discussed.

so it'll have almost no
degeneration on the oscillations. I changed from a zener to TL430,
and
some pot that will handle a bit of current. I have to get the TL430
in
there somewhere. I'm working on it.

;-) Thanks.

[snip]

In article <10u06sd6nig276e_at_corp.supernews.com>,
"Watson A.Name - \"Watt Sun wrote:

"The Phantom" <phantom_at_aol.com> wrote in message

......You will have gotten rid of a big capacitor and possible
source of long time constant behavior, and have an easily
adjustable, low impedance bias supply.

I could just use the 9V supply and a resistor and zener to do
that, instead. Same diff and it saves batteries.

That capacitor *has* to be got rid of. There are other
problems as well though. The low voltage across S-D
is running the jfet in a place where it has a low output
impedance, and lots of distortion. The even-harmonic
components in the distortion is probably accumulating on
the capacitor and shifting the bias point, away from
oscillation.... a sort of leisurely squegging.

If you have to stay with a 9v supply, then a folded cascode
circuit could take away a lot of the fundamental problems.
As below, LTSpice says it works ok.


+--------------------------------------+9V
| |
\ \
/2k /1k5
\ \
_|_ 0.15mA approx, |
\_/ +--<-----------------------------+<--7V
| |/e so Rin= 180 ohms approx. |
+---|pnp | Id= 1.2mA
| |\ | Rd= 5k.
| | R2 R R |--+
| +--/\/\--+--/\/\--+--/\/\--+-->|J1,2N3819
| | 135k | 150k | 150k | |--+
| | +| +| +| |<--4.7V
\ \R1 ===C ===C ===C |
/1k6 /15k | | | +----+
\ \ | | | \_|_ |
| | | | | ZD1/_\ |
| | | | | 4v7 | |
| +--------+--------+--------+------+0V |
| R1=15k, and R1+R2 = R always. |
+-------------------------------------------+

The effective Drain load is R1, but the folded cascode
allows a high jfet current (high gm) and yet at the same
time have a high value of load resistance. The 180 ohm
input resistance at the pnp emitter means that about 90%
of the AC current from the jfet goes down the transistor
and it means that the AC Vd-s voltage is almost zero
(which keeps the distortion low).

The lagging phase-shifter allows a dc-coupled negative
feedback type of self-biassing. The dc voltage across R1
will always be 4.7V minus whatever Vg-s the jfet needs for
an Id of 1.2mA. The gm of the jfet has to be about 2.2mA/V
for the circuit to oscillate.

With the generic 2N3819, LTSpice gives a dc-operating point
of about 2.6V across R1, and an AC oscillation voltage of
4.8V pk-pk. The sinewave looks reasonable, just flat bottoms
at about 0.4V, as the transistor runs out of current.

For the lagging phase shifter, F= root-6/2.pi.R.C and with
1uF caps the simulated frequency is 2.59Hz.

It takes a few hundred seconds for the oscillation to come
up and finally stabilise.

"Rich Grise" <richgrise_at_example.net> wrote in message

Hey, Rich. You live in Whittier? Have the rains filled up Whittier
Narrows and turned it and the recreation area into a giant mudflat?
:-P

I do live in Whittier, but I don't get out much; in fact this is the
first
I've heard of "The Whitter Narrows" - I don't even know where it is.

Hard to miss, since it's as big as the whole city. Here's a map. The
green area at the top is the recreation area, golf course, lakes, etc.
Roughly the 60 Fwy and Rosemead. The bottom or south end of the green is
the big dam.
http://maps.yahoo.com/maps_result?ed=M7tNO.p_0TqT&csz=whittier+junction%
2C+calif&country=us&new=1&name=&qty=

Ah. Gotcha. I haven't been through there since before the raining started.

Jim Thompson <thegreatone_at_example.com> wrote:

Come on, Tony, you done gone and ruined this whole thread by
introducing some actual engineering thought into the process ;-)

Sorry Jim.......

The folded cascode (with dc feedback bias) was my favorite
circuit when using a single jfet, it evades all sorts of
problems. By ratio'ing the currents it is even possible
to do the self-bias for constant gm, as per the Siliconix
app note TA70-2.

In this case, getting 29x off a 9Vdc rail is possible,
but still a little too marginal for comfort.

Tony Williams' JFET phase-shift oscillator. Very nice.

. ,---------------------------------------+--- 9V
. | |
. \ \
. /2k /1k5
. \ \
. _|_ 0.15mA approx, |
. \_/ +--<------------------------------+ <--7V
. | |/e so Rin= 180 ohms approx. |
. +---| pnp | Id= 1.2mA
. | |\ | Rd= 5k.
. | | R2 R R |--+
. | +--/\/\--+--/\/\--+--/\/\--+-->| J1, 2N3819
. | | 135k | 150k | 150k | |--+
. | | +| +| +| | <--4.7V
. \ \R1 === === === |
. /1k6 /15k | C | C | C +----,
. \ \ | | | \_|_ |
. | | | | | ZD1/_\ |
. | | | | | 4v7 | |
. | +--------+--------+--------+------+0V |
. | R1=15k, and R1+R2 = R always. |
. '--------------------------------------------'

Where do you take the output? With JFET source follower from
the pnp output? Or from J1's gate signal for lower distortion?
With a cc pulldown? What's the ac swing there, 2 to 2.5 Vpp?

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10 uF,
and the three resistors to common are 150k each. The FET is a MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


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