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What use is the 3 delay number: min:typical:max?

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elektroda.net NewsGroups Forum Index - Verilog Language - What use is the 3 delay number: min:typical:max?

Robert Willy
Guest

Mon Mar 19, 2018 3:45 am   



Hi,
I run below code snippet, which is copied from on line tutorial.
it gives 3 delay number: #(1:2:3). I only see the typical delay number (2)
is in effect in the simulation. What use is the other min and max numbers?


Thanks,




module tri_buf_using_assign_delays();
reg data_in, enable;
wire pad;

assign #(1:2:3) pad = (enable) ? data_in : 1'bz;

initial begin
$monitor ("ENABLE = %b DATA : %b PAD %b",enable, data_in,pad);
#10 enable = 0;
#10 data_in = 1;
#10 enable = 1;
#10 data_in = 0;
#10 enable = 0;
#10 $finish;
end

endmodule

Johann Klammer
Guest

Mon Mar 19, 2018 5:45 pm   



On 03/19/2018 03:28 AM, Robert Willy wrote:
Quote:
Hi,
I run below code snippet, which is copied from on line tutorial.
it gives 3 delay number: #(1:2:3). I only see the typical delay number (2)
is in effect in the simulation. What use is the other min and max numbers?


Thanks,




module tri_buf_using_assign_delays();
reg data_in, enable;
wire pad;

assign #(1:2:3) pad = (enable) ? data_in : 1'bz;

initial begin
$monitor ("ENABLE = %b DATA : %b PAD %b",enable, data_in,pad);
#10 enable = 0;
#10 data_in = 1;
#10 enable = 1;
#10 data_in = 0;
#10 enable = 0;
#10 $finish;
end

endmodule

You can choose which one to use.
iverilog has the -T switch for that.
Of course it is not very reperesentative of the real thing.
The value between min and max should probably be X
but none of those simulators does that.
You can massage the vcd file, tho'.
there's a program here:
<http://members.aon.at/~aklamme4/files.html>
(the fourth item)

unfrostedpoptart
Guest

Tue Mar 20, 2018 7:45 pm   



On Sunday, March 18, 2018 at 7:28:29 PM UTC-7, Robert Willy wrote:
Quote:
Hi,
I run below code snippet, which is copied from on line tutorial.
it gives 3 delay number: #(1:2:3). I only see the typical delay number (2)
is in effect in the simulation. What use is the other min and max numbers?


This is pretty much only for gate-level simulation after synthesis, placement, and routing where you have a back-annotated netlist and want to check your design at various voltage, temperature, and process corners.

By default, the simulator is using the typical number.

David

elektroda.net NewsGroups Forum Index - Verilog Language - What use is the 3 delay number: min:typical:max?

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