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What meaning is '-' in '(((i-1)*3 + (j-1)) * 18)+17 -:18'?

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Guest

Tue Aug 26, 2014 2:29 pm   



Hi,

I read the following code on line. The '-' sign in the below code puzzles me a
lot. Could you explain it to me?


Thanks,




..............
module top;

wire[17:0]A[1:3][1:3]; // the matrices
wire[17:0]B[1:3][1:3];
wire[17:0]C[1:3][1:3];

wire[(9*1Cool-1:0] Abits; // bit-decomposed versions of the above
wire[(9*1Cool-1:0] Bbits;
wire[(9*1Cool-1:0] Cbits;

genvar i,j;

// set A and B with initial values
generate
for(i=0; i<3; i=i+1)
for(j=0; j<3; j=j+1) begin
assign A[i+1][j+1] = i*3 + j;
assign B[i+1][j+1] = i*3 + j + 1;
end
endgenerate

// decompose A and B, set C
generate
for(i=1; i<=3; i=i+1)
for(j=1; j<=3; j=j+1) begin
assign Abits[(((i-1)*3 + (j-1)) * 1Cool+17 -:18] = A[i][j];
assign Bbits[(((i-1)*3 + (j-1)) * 1Cool+17 -:18] = B[i][j];
assign C[i][j] = Cbits[(((i-1)*3 + (j-1)) * 1Cool+17 -:18];
end
endgenerate


Guest

Wed Aug 27, 2014 11:42 am   



On Tuesday, August 26, 2014 8:29:45 AM UTC-4, rxj...@gmail.com wrote:
> Hi,

Excuse me. I did not make it clear. I mean the meaning of '-:' (before 1Cool in
this line:

assign Abits[(((i-1)*3 + (j-1)) * 1Cool+17 -:18] = A[i][j];


Could you help me on that? Thanks,

Allan Herriman
Guest

Wed Aug 27, 2014 4:50 pm   



On Wed, 27 Aug 2014 02:42:53 -0700, rxjwg98 wrote:

Quote:
On Tuesday, August 26, 2014 8:29:45 AM UTC-4, rxj...@gmail.com wrote:
Hi,

Excuse me. I did not make it clear. I mean the meaning of '-:' (before
1Cool in this line:

assign Abits[(((i-1)*3 + (j-1)) * 1Cool+17 -:18] = A[i][j];


Could you help me on that? Thanks,


That ugly feature is called "indexed part select" and was introduced to
the language in the 2001 revision.

It allows you to extract a slice of a vector using an index that can be
an expression. The slice width (in this case 1Cool must be fixed at
compile time.
It is another way of defining a multiplexer.

Abits must have been declared with a descending range, e.g. [100:0].

There is a corresponding +: that works on arrays with ascending ranges,
e.g. [0:100].

Google for examples.

Regards,
Allan

unfrostedpoptart
Guest

Fri Aug 29, 2014 3:21 am   



On Wednesday, August 27, 2014 3:50:12 AM UTC-7, Allan Herriman wrote:
Quote:
On Wed, 27 Aug 2014 02:42:53 -0700, rxjwg98 wrote:
Excuse me. I did not make it clear. I mean the meaning of '-:' (before 1Cool in this line:
assign Abits[(((i-1)*3 + (j-1)) * 1Cool+17 -:18] = A[i][j];

That ugly feature is called "indexed part select" and was introduced to the language in the 2001 revision.
It allows you to extract a slice of a vector using an index that can be an expression. The slice width (in this case 1Cool must be fixed at compile time.


It's not an ugly feature. It's an incredibly useful feature to fix a problem with Verilog '95 that only allow constant bit-slices. To access a slice at a variable offset required writing for loops and accessing the bits one at a time.

Here's a good explanation of the operator: http://stackoverflow.com/questions/18067571/indexing-vectors-and-arrays-with

Quote:
Abits must have been declared with a descending range, e.g. [100:0].
There is a corresponding +: that works on arrays with ascending ranges,

e.g. [0:100]


That is total nonsense! It has nothing to do with the direction of the ranges. One just lets you specify the MSB of the slice and the width while the other specifies the LSB of the slice and the width. Both work with vectors defined increasing or decreasing.

David

Allan Herriman
Guest

Fri Aug 29, 2014 3:44 pm   



On Thu, 28 Aug 2014 18:21:16 -0700, unfrostedpoptart wrote:

Quote:
On Wednesday, August 27, 2014 3:50:12 AM UTC-7, Allan Herriman wrote:
On Wed, 27 Aug 2014 02:42:53 -0700, rxjwg98 wrote:
Excuse me. I did not make it clear. I mean the meaning of '-:'
(before 1Cool in this line:
assign Abits[(((i-1)*3 + (j-1)) * 1Cool+17 -:18] = A[i][j];

That ugly feature is called "indexed part select" and was introduced to
the language in the 2001 revision.
It allows you to extract a slice of a vector using an index that can be
an expression. The slice width (in this case 1Cool must be fixed at
compile time.

It's not an ugly feature.


Ugly is in the eye of the beholder. It fixes an error in the earlier
definition of the language, and in that sense it might be seen as
something good.

There was no need to introduce a new syntactic element (the :- ) though -
a simpler (and arguably more intuitive) way would have been just to
remove the requirement that the slice bounds be constant. Other
languages (e.g. VHDL) have no problem doing it that way.
I don't recall why the language committee didn't adopt that approach.

Quote:
Abits must have been declared with a descending range, e.g. [100:0].
There is a corresponding +: that works on arrays with ascending ranges,

e.g. [0:100]

That is total nonsense! It has nothing to do with the direction of the
ranges. One just lets you specify the MSB of the slice and the width
while the other specifies the LSB of the slice and the width. Both work
with vectors defined increasing or decreasing.


Indeed it is nonsense. I really should read the LRM from time to time.
Thanks for the correction.

Allan

unfrostedpoptart
Guest

Sun Aug 31, 2014 7:53 pm   



On Friday, August 29, 2014 2:44:23 AM UTC-7, Allan Herriman wrote:
Quote:
On Thu, 28 Aug 2014 18:21:16 -0700, unfrostedpoptart wrote:

Ugly is in the eye of the beholder. It fixes an error in the
earlier definition of the language, and in that sense it might
be seen as something good.

There was no need to introduce a new syntactic element (the :-
) though - a simpler (and arguably more intuitive) way would
have been just to remove the requirement that the slice bounds
be constant. Other languages (e.g. VHDL) have no problem
doing it that way. I don't recall why the language committee
didn't adopt that approach.


Two issues here. First, as my instructor repeated over and over
in the Advanced SystemVerilog Design and Verification class I
just took at Cadence, nothing new / changed in SV should at all
change existing Verilog code or tons of current stuff could
break. That's why they used a new construct.

Also, the new construct allows the offset to be variable now but
not the slice width! If you just allowed A and B to be variable
in [A:B], it would be much less obvious that width==(A-B-1) must
be constant. This could make code more confusing to write/read
and for the compiler to statically verify.

Quote:
That is total nonsense! It has nothing to do with the
direction of the ranges. One just lets you specify the MSB of
the slice and the width while the other specifies the LSB of
the slice and the width. Both work with vectors defined
increasing or decreasing. Indeed it is nonsense. I really
should read the LRM from time to time.


I find reading the LRM just gives me headaches! It also
virtually never says anything about how or why on and topic.

> Thanks for the correction.

Not a problem. I'm starting to do verification with classes and
UVM and will certainly have lots of mistakes in upcoming weeks!

David


Guest

Mon Apr 22, 2019 10:45 am   



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[1]: https://www.whatmeaningis.com/

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