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what is the reason of this error??

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Youjung Hong
Guest

Tue Jan 06, 2015 6:06 am   



I am making eeprom on Actel A3PE3000 board.
when I place and route ports, I got this errors.
I don't know what is the reason.

Here is the error report.

***** Layout Variables *********************************************

Mode: TIMING_DRIVEN
Power-driven Layout: OFF
Incremental Placement: OFF
Incremental Route: OFF



Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.


Planning global net placement...
Error: PLC004: No legal global assignment could be found. Some global nets have shared
instances, requiring them to be assigned to overlapping global regions.

Global Nets Whose Drivers Are Limited to Quadrants or Which Have No Valid Locations:

|--------------------------------------------|
|Global Net |Valid Driver Locations |
|--------------------------------------------|
|CLK_c |(None)
|--------------------------------------------|
|RST_c |(None)
|--------------------------------------------|

Info: Consider relaxing the constraints for these nets by removing region constraints,
unassigning fixed cells and I/Os, relaxing I/O bank assignments, or using input
buffers without hardwired pad connections.
Error: PLC003: No legal global assignment could be found because of complex region and/or IO
technology constraints.
Error: PLC005: Automatic global net placement failed.
INFO: See the GlobalNet Report from the Reports option of the Tools menu for information about
the global assignment.

The Layout command failed ( 00:00:01 )

The Layout command failed ( 00:00:02 )
Error: Failure when executing Tcl script. [ Line 18 ]

The Execute Script command failed ( 00:00:05 )
Warning: The database was closed without a save, modifications are lost
Design closed.

Brian Drummond
Guest

Tue Jan 06, 2015 3:48 pm   



On Mon, 05 Jan 2015 20:06:03 -0800, Youjung Hong wrote:

Quote:
I am making eeprom on Actel A3PE3000 board.
when I place and route ports, I got this errors.
I don't know what is the reason.

Here is the error report.

***** Layout Variables *********************************************

Mode: TIMING_DRIVEN Power-driven Layout: OFF Incremental Placement: OFF
Incremental Route: OFF



Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.


Planning global net placement...
Error: PLC004: No legal global assignment could be found.


I hope you haven't laid out the PCB yet.

Quote:

|--------------------------------------------|
|Global Net |Valid Driver Locations |
|--------------------------------------------|
|CLK_c |(None)
|--------------------------------------------|
|RST_c |(None)
|--------------------------------------------|


Your pin assignment is incorrect. While you have apparently assigned CLK_c
and RST_c to "global" pins, that is not good enough, because, incredibly,
"global" pins are not actually global. You need "chip global" pins as
opposed to the "quadrant global" pins you are apparently using now (which
the name implies can only access 1/4 of the device).

This unique interpretation of the word "global" nearly caught me out
too ... fortunately I mistrust the tools enough to have insisted on a PAR
run before board layout...

The data sheet I'm looking at says (section 3-2), User Pins
"All inputs labeled GC/GF are direct inputs into the quadrant clocks. For
example, if GAA0 is used for an input, GAA1 and GAA2 are no longer
available for input to the quadrant globals. "
and
"All inputs labeled GC/GF are direct inputs into
the chip-level globals, and the rest are connected
to the quadrant globals"

Unfortunately this seems to contradict itself, probably a cut&paste
error, and I can't be bothered to find another datasheet. But it means
you have to select pins named (probably) GCnn or GFnn to get truly global
clock and reset signals.

- Brian


Guest

Mon Apr 09, 2018 5:45 pm   



On Tuesday, 6 January 2015 14:49:03 UTC+1, Brian Drummond wrote:

Quote:
Your pin assignment is incorrect. While you have apparently assigned CLK_c
and RST_c to "global" pins, that is not good enough, because, incredibly,
"global" pins are not actually global. You need "chip global" pins as
opposed to the "quadrant global" pins you are apparently using now (which
the name implies can only access 1/4 of the device).


Thank you so much Brian.
I had little hope that googling this error would actually find me a solution, but this was pretty much the only one I found.
I'm working with a Microsemi IGLOO Nano, and even reading the IGLOO nano FPGA Fabric User Guide didn't really help me, partly beacuse - like you mention - the word "global" feels very misused, and the info is spread out and addresses all devices at once, some of which don't even have global quadrant clocks etc.

/Henrik


Guest

Tue May 08, 2018 10:45 am   



On Monday, April 9, 2018 at 9:34:09 PM UTC+5:30, dahe...@gmail.com wrote:
Quote:
On Tuesday, 6 January 2015 14:49:03 UTC+1, Brian Drummond wrote:

Your pin assignment is incorrect. While you have apparently assigned CLK_c
and RST_c to "global" pins, that is not good enough, because, incredibly,
"global" pins are not actually global. You need "chip global" pins as
opposed to the "quadrant global" pins you are apparently using now (which
the name implies can only access 1/4 of the device).

Thank you so much Brian.
I had little hope that googling this error would actually find me a solution, but this was pretty much the only one I found.
I'm working with a Microsemi IGLOO Nano, and even reading the IGLOO nano FPGA Fabric User Guide didn't really help me, partly beacuse - like you mention - the word "global" feels very misused, and the info is spread out and addresses all devices at once, some of which don't even have global quadrant clocks etc.

/Henrik


Did Anyone found the solution for this? I am still getting this error in my project.

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