Sun Dec 23, 2018 8:45 pm
On 23/12/2018 17:56, gnuarm.deletethisbit_at_gmail.com wrote:
On Sunday, December 23, 2018 at 11:43:29 AM UTC-5, HT-Lab wrote:
To do a bit of nitpicking, they do (have to for timing optimisations)
and I am not talking about a wire-load model. High-end synthesis tool
offer what is called Physical Aware Synthesis (PAS). What they do is to
run an internal placer (or use the P&R vendors version) and use that to
estimate the timing to a surprising degree of accuracy. Apparently they
do not need to run the actual routing as this is not required for a good
I'd love to know more about that. If they don't know the routing in the end design how can they know the timing?
Unfortunately I don't have much info on this, perhaps somebody else on
this ng knows how it all works. I suspect that placement will allow you
to identified the long tracks and congested areas, a wire-load model can
then be used for final bits.
>I don't know how you would "estimate" the timing. In particular, the timing required by wave-pipelining would be much more detailed than in regular design requiring limits on the minimum AND maximum delays of *each path*, not just logic.
I agree, but I was not talking about wave-pipelining, just regular