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KJ
Guest

Sun Dec 16, 2018 3:45 pm   



On Saturday, December 15, 2018 at 11:28:47 PM UTC-5, gnuarm.del...@gmail.com
Quote:

I have no idea what "cut off" means.

Weng is upset that his original three state machine can actually be implemented with a single state. States 'S1' and 'S2' in that sense were cut off because they were useless.


Quote:

If you are actually talking about the next_state equations rather than what appeared to be an intermediate signal that may or may not exist in any given design, what are your questions exactly?

I don't think he has any actual questions. Weng tends to present claims that tend to be false but insists they are true. That's his delusion to resolve.


Weng also tends to post code that is not representative of the code that he bases his claim upon. That was the case here where he based his claim on code that did not have the "elsif C2" branch in it. Take that branch out and you have a one-hot encoded single input state machine which has already been pointed out to him to be the special case where his statement is in some sense true. However, the 'S0_C1' signal that he crows about is really just the next state...so what?

Kevin

Weng Tianxiang
Guest

Sun Dec 16, 2018 7:45 pm   



On Sunday, December 16, 2018 at 6:16:40 AM UTC-8, KJ wrote:
Quote:
On Saturday, December 15, 2018 at 11:28:47 PM UTC-5, gnuarm.del...@gmail.com

I have no idea what "cut off" means.

Weng is upset that his original three state machine can actually be implemented with a single state. States 'S1' and 'S2' in that sense were cut off because they were useless.


If you are actually talking about the next_state equations rather than what appeared to be an intermediate signal that may or may not exist in any given design, what are your questions exactly?

I don't think he has any actual questions. Weng tends to present claims that tend to be false but insists they are true. That's his delusion to resolve.

Weng also tends to post code that is not representative of the code that he bases his claim upon. That was the case here where he based his claim on code that did not have the "elsif C2" branch in it. Take that branch out and you have a one-hot encoded single input state machine which has already been pointed out to him to be the special case where his statement is in some sense true. However, the 'S0_C1' signal that he crows about is really just the next state...so what?

Kevin


I will publish my research result in patent application form in a month or so, systematically describing a new tool every hardware engineer here will benefit from my invention, providing more than 10 circuits.

I don't see any benefits for continuing debates here.

Weng

Thomas Stanka
Guest

Wed Dec 19, 2018 5:45 pm   



Hello,

Am Donnerstag, 13. Dezember 2018 14:45:47 UTC+1 schrieb Weng Tianxiang:
> What is the name of the circuit structure that generates a state machine's jumping signals?

transition (function) logic

Maybe it would be helpful for you to read
en.wikipedia.org/wiki/Finite-state_machine

A FSM can be as simple as a counter from 0 to 1 (modulo 2) or can be a complete fpga design. It is often seen that someone claims this term only for "explicite expressed" FSMs using eg an enumerated type in VHDL, but in general all needed for a FSM is to have at 2+ states, any kind of input (clock alone is sufficient) to activate switching between those states (based on a defined transition function) plus any output that is depending on state alone or state and input.

Especially the kind of coding structure used (1 process, 2 process, 3 process) as well as the question if the states are enumerated type or std_logic_vectors are not relevant.

You can draw a statemachine with bubble diagram which contains a bubble for each state and an arrow for each transition. In this abstraction you have a "signal" for each state transition.

Quote:
type State_Type is ( S0, S1, ...);
signal WState, WState_NS : State_Type;

a : process(CLK)
begin
if rising_edge(CLK) then
if SINI = '1' then
WState <= S0;

else
WState <= WState_NS;
end if;
end if;
end process;

b : process(all)
begin
case WState is
when S0 =
if C1 then
WState_NS <= S1;

elsif C2 then
WState_NS <= S2;

else
WState_NS <= S0;
end if;
...;
end case;
end process;

Now a synthesizer must generate a signal S0_C1 as follows

S0_C1 <= not SINI and WState = S0 and C1;


Why?

The code is equivalent to

process (Clk)
if SINI ='1' then
WState <= S0;
else
case WState is

Thomas Stanka
Guest

Wed Dec 19, 2018 6:45 pm   



Am Donnerstag, 13. Dezember 2018 14:45:47 UTC+1 schrieb Weng Tianxiang:
> What is the correct name?

transition (function) logic

Maybe it would be helpful for you to read
en.wikipedia.org/wiki/Finite-state_machine

A FSM can be as simple as a counter from 0 to 1 (modulo 2) or can be a complete fpga design. It is often seen that someone claims this term only for "explicite expressed" FSMs using eg an enumerated type in VHDL, but in general all needed for a FSM is to have at 2+ states, any kind of input (clock alone is sufficient) to activate switching between those states (based on a defined transition function) plus any output that is depending on state alone or state and input.

Especially the kind of coding structure used (1 process, 2 process, 3 process) as well as the question if the states are enumerated type or std_logic_vectors are not relevant.

You can draw a statemachine with bubble diagram which contains a bubble for each state and an arrow for each transition. In this abstraction you have a "signal" for each state transition.

Quote:
type State_Type is ( S0, S1, ...);
signal WState, WState_NS : State_Type;

a : process(CLK)
begin
if rising_edge(CLK) then
if SINI = '1' then
WState <= S0;

else
WState <= WState_NS;
end if;
end if;
end process;

b : process(all)
begin
case WState is
when S0 =
if C1 then
WState_NS <= S1;

elsif C2 then
WState_NS <= S2;

else
WState_NS <= S0;
end if;
...;
end case;
end process;

Now a synthesizer must generate a signal S0_C1 as follows

S0_C1 <= not SINI and WState = S0 and C1;


Why?

The code is equivalent to

process (Clk)
if SINI ='1' then
WState <= S0;
else
case WState is
when S0 =>
if C1 then
WState_NS <= S1;
elsif C2 then
WState_NS <= S2;
else
WState_NS <= S0;
end case;
end if;

This equivalent code will not necesseary generate a signal "xx <= not SINI and WState = S0 and C1" after synthesis. It will have this signal in an synthesis intermediate state but after logic optimisation this signal can be removed in favor of simplified functionality depending on the complete FSM transition logic.

bye Thomas


Guest

Sat Dec 22, 2018 8:45 pm   



On Sunday, December 16, 2018 at 9:16:40 AM UTC-5, KJ wrote:
Quote:
On Saturday, December 15, 2018 at 11:28:47 PM UTC-5, gnuarm.del...@gmail.com

I have no idea what "cut off" means.

Weng is upset that his original three state machine can actually be implemented with a single state. States 'S1' and 'S2' in that sense were cut off because they were useless.


If you are actually talking about the next_state equations rather than what appeared to be an intermediate signal that may or may not exist in any given design, what are your questions exactly?

I don't think he has any actual questions. Weng tends to present claims that tend to be false but insists they are true. That's his delusion to resolve.

Weng also tends to post code that is not representative of the code that he bases his claim upon. That was the case here where he based his claim on code that did not have the "elsif C2" branch in it. Take that branch out and you have a one-hot encoded single input state machine which has already been pointed out to him to be the special case where his statement is in some sense true. However, the 'S0_C1' signal that he crows about is really just the next state...so what?


Isn't Weng the same guy who couldn't understand that for wave pipelining to work delays had to be bracketed rather than the max spec they give in FPGAs?

I seem to recall a fairly long argument about that fact. I wonder if he ever got any sort of a patent out of that?

Rick C.

Tesla referral code --+ https://ts.la/richard11209
Get 6 months of free supercharging

Weng Tianxiang
Guest

Sat Dec 22, 2018 11:45 pm   



Hi Thomas,

> S0_C1 <= not SINI and WState = S0 and C1;

"This equivalent code will not necessarily generate a signal "xx <= not SINI and WState = S0 and C1" after synthesis. It will have this signal in an synthesis intermediate state but after logic optimisation this signal can be removed in favor of simplified functionality depending on the complete FSM transition logic. "

You are right. I never say the S0_C1 will be the final logic, but says that the signal must appear during the synthesization.

Rick,

1. Systematic method of coding wave-pipelined circuits in HDL

Patent #: 9-747-252 B2
Issue date: 2017-08-29
Allowance date: 2017-06-27
Filing data: 02/05/2016

2. Apparatus of wave-pipelined circuits
Patent #: 9-575-929 B2
Issue date: 2017-02-21
Allowance date: 2016-12-21
Filing data: 02/05/2016

3. Systematic method of synthesizing wave-pipelined circuits in HDL

Patent #: 9-734-127 B2
Issue date: 2017-08-15
Allowance date: 2017-06-19
Filing data: 02/05/2016

I think someday they will be introduced into HDL standard.

Google reviewed the applications since 2015/02/18, and finally made a rejection for the offer on 2018/03/16, 7 months after they became patents.

Weng


Guest

Sun Dec 23, 2018 4:45 am   



On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote:
Quote:
Hi Thomas,

S0_C1 <= not SINI and WState = S0 and C1;

"This equivalent code will not necessarily generate a signal "xx <= not SINI and WState = S0 and C1" after synthesis. It will have this signal in an synthesis intermediate state but after logic optimisation this signal can be removed in favor of simplified functionality depending on the complete FSM transition logic. "

You are right. I never say the S0_C1 will be the final logic, but says that the signal must appear during the synthesization.

Rick,

1. Systematic method of coding wave-pipelined circuits in HDL

Patent #: 9-747-252 B2
Issue date: 2017-08-29
Allowance date: 2017-06-27
Filing data: 02/05/2016

2. Apparatus of wave-pipelined circuits
Patent #: 9-575-929 B2
Issue date: 2017-02-21
Allowance date: 2016-12-21
Filing data: 02/05/2016

3. Systematic method of synthesizing wave-pipelined circuits in HDL

Patent #: 9-734-127 B2
Issue date: 2017-08-15
Allowance date: 2017-06-19
Filing data: 02/05/2016

I think someday they will be introduced into HDL standard.

Google reviewed the applications since 2015/02/18, and finally made a rejection for the offer on 2018/03/16, 7 months after they became patents.


I'm not interested in reading the patents. But if you wish to explain the point of your patents, the utility as it were, in a way that we can understand, I would like to hear it. From the discussions we had you didn't understand the futility of trying to use these patents in FPGAs. While they may be useful in ASICs, I don't believe you ever explained what you were actually patenting.

Rick C.

Tesla referral code -+- https://ts.la/richard11209
Get 6 months of free supercharging

Weng Tianxiang
Guest

Sun Dec 23, 2018 6:45 am   



Rick,

Here are the main points about my inventions on wave-pipelining circuits:

1. All wave-pipelining circuits will be written in such a code if they were one-cycle logic.

2. Use a link statement linking your wave-pipeling circuit with one of 3 entities I have developed as a wave-pipelining circuit library.

3. A synthesizer generates the wave-pipelined circuit with one or two determined wave-constants passing to the entity.

4. There is no other logic to write.

5. It is specially useful for FPGA if the new HDL rules are accepted into new HDL standard.

6. Theory base: all wave-pipelining circuits are different in their 1-cycle logic, but other logic relating to the wave-pipelining parts are the same and classified into 3 categories that leads to 3 entities.

7. Example circuits: FFT-16; floating A*B --> C;

Weng


Guest

Sun Dec 23, 2018 7:45 am   



On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote:
Quote:
Rick,

Here are the main points about my inventions on wave-pipelining circuits:

1. All wave-pipelining circuits will be written in such a code if they were one-cycle logic.

2. Use a link statement linking your wave-pipeling circuit with one of 3 entities I have developed as a wave-pipelining circuit library.

3. A synthesizer generates the wave-pipelined circuit with one or two determined wave-constants passing to the entity.

4. There is no other logic to write.

5. It is specially useful for FPGA if the new HDL rules are accepted into new HDL standard.

6. Theory base: all wave-pipelining circuits are different in their 1-cycle logic, but other logic relating to the wave-pipelining parts are the same and classified into 3 categories that leads to 3 entities.

7. Example circuits: FFT-16; floating A*B --> C;

Weng


So what software handles the timing analysis and balances the delays???

If you are expecting the synthesis software to do the heavy lifting of timing analysis, what exactly do your libraries do? What are your three entities?

BTW, do you realize the synthesis software doesn't actually know the timing of an FPGA circuit??? Timing is determined as much by the routing as it is the logic elements. So it is up to the chip vendor's place and route tools to get that right. This would not be an easy task to accomplish.

And of course all of this ignores the fact that minimum delays are just as important as maximum delays in FPGA logic. It is hard to tell if you could ever get this to work across the three variables of timing, process, voltage and temperature. Every chip will vary. Each board with slightly different PS voltages will vary. Every operating temperature will vary. For a wave pipeline to work all of the inputs to the delay equation have to result in a very small window of delay variation.

How do you plan to control any of that?

Rick C.

Tesla referral code -++ https://ts.la/richard11209
Get 6 months of free supercharging -++

Weng Tianxiang
Guest

Sun Dec 23, 2018 3:45 pm   



On Saturday, December 22, 2018 at 10:34:01 PM UTC-8, gnuarm.del...@gmail.com wrote:
Quote:
On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote:
Rick,

Here are the main points about my inventions on wave-pipelining circuits:

1. All wave-pipelining circuits will be written in such a code if they were one-cycle logic.

2. Use a link statement linking your wave-pipeling circuit with one of 3 entities I have developed as a wave-pipelining circuit library.

3. A synthesizer generates the wave-pipelined circuit with one or two determined wave-constants passing to the entity.

4. There is no other logic to write.

5. It is specially useful for FPGA if the new HDL rules are accepted into new HDL standard.

6. Theory base: all wave-pipelining circuits are different in their 1-cycle logic, but other logic relating to the wave-pipelining parts are the same and classified into 3 categories that leads to 3 entities.

7. Example circuits: FFT-16; floating A*B --> C;

Weng

So what software handles the timing analysis and balances the delays???

If you are expecting the synthesis software to do the heavy lifting of timing analysis, what exactly do your libraries do? What are your three entities?

BTW, do you realize the synthesis software doesn't actually know the timing of an FPGA circuit??? Timing is determined as much by the routing as it is the logic elements. So it is up to the chip vendor's place and route tools to get that right. This would not be an easy task to accomplish.

And of course all of this ignores the fact that minimum delays are just as important as maximum delays in FPGA logic. It is hard to tell if you could ever get this to work across the three variables of timing, process, voltage and temperature. Every chip will vary. Each board with slightly different PS voltages will vary. Every operating temperature will vary. For a wave pipeline to work all of the inputs to the delay equation have to result in a very small window of delay variation.

How do you plan to control any of that?

Rick C.

Tesla referral code -++ https://ts.la/richard11209
Get 6 months of free supercharging -++


Rick,

Intel first finished its 8087 chip using the wave-pipelining technology. Nowadays every company has the technology. Based on my knowledge, even Chinese Huawei cellphone company uses the technology comfortably.

You are right that Xilinx and Altera also have the potential to control the technology. Nowadays any variations of temperatures, routine delays and voltages are well known and calculated.

Weng

KJ
Guest

Sun Dec 23, 2018 4:45 pm   



On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote:
Quote:

I think someday they will be introduced into HDL standard.

Even if the patents are useful they wouldn't make it into any language standard...because they are patented. You don't understand how language standards happen, they are not going to take in anything claimed as proprietary.


Quote:
Google reviewed the applications since 2015/02/18, and finally made a rejection for the offer on 2018/03/16, 7 months after they became patents.

So you're saying that Google reviewed your patents and did not find any value for them as a company. If the patents are so useful shouldn't you be mentioning which companies DID license your patents?


Kevin

KJ
Guest

Sun Dec 23, 2018 4:45 pm   



On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote:
Quote:

You are right. I never say the S0_C1 will be the final logic, but says that the signal must appear during the synthesization.

Again you are mistaken except for the special case of a one-hot encoded single input state machine. Post the source code for something other than that type of state machine that you have actually used along with the synthesis result that produces the S0_C1 signal to provide evidence otherwise you're just making baseless, incorrect statements again.


Kevin

HT-Lab
Guest

Sun Dec 23, 2018 5:45 pm   



On 23/12/2018 06:33, gnuarm.deletethisbit_at_gmail.com wrote:
Quote:
On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote:
Rick,
...

So what software handles the timing analysis and balances the delays???

If you are expecting the synthesis software to do the heavy lifting of timing analysis, what exactly do your libraries do? What are your three entities?

BTW, do you realize the synthesis software doesn't actually know the timing of an FPGA circuit???


To do a bit of nitpicking, they do (have to for timing optimisations)
and I am not talking about a wire-load model. High-end synthesis tool
offer what is called Physical Aware Synthesis (PAS). What they do is to
run an internal placer (or use the P&R vendors version) and use that to
estimate the timing to a surprising degree of accuracy. Apparently they
do not need to run the actual routing as this is not required for a good
estimate.

>Timing is determined as much by the routing as it is the logic elements.

I would say that for modern FPGA's the routing is normally the timing
killer (on my designs routing delay >2x logic delay). I guess this is
the reason products like Plunify (no affiliation) are so successful.

Quote:
So it is up to the chip vendor's place and route tools to get that right. This would not be an easy task to accomplish.

And of course all of this ignores the fact that minimum delays are just as important as maximum delays in FPGA logic. It is hard to tell if you could ever get this to work across the three variables of timing, process, voltage and temperature. Every chip will vary. Each board with slightly different PS voltages will vary. Every operating temperature will vary. For a wave pipeline to work all of the inputs to the delay equation have to result in a very small window of delay variation.
How do you plan to control any of that?

Rick C.

Tesla referral code -++ https://ts.la/richard11209
Get 6 months of free supercharging -++


Regards,
Hans
www.ht-lab.com


Guest

Sun Dec 23, 2018 7:45 pm   



On Sunday, December 23, 2018 at 8:58:36 AM UTC-5, Weng Tianxiang wrote:
Quote:
On Saturday, December 22, 2018 at 10:34:01 PM UTC-8, gnuarm.del...@gmail.com wrote:
On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote:
Rick,

Here are the main points about my inventions on wave-pipelining circuits:

1. All wave-pipelining circuits will be written in such a code if they were one-cycle logic.

2. Use a link statement linking your wave-pipeling circuit with one of 3 entities I have developed as a wave-pipelining circuit library.

3. A synthesizer generates the wave-pipelined circuit with one or two determined wave-constants passing to the entity.

4. There is no other logic to write.

5. It is specially useful for FPGA if the new HDL rules are accepted into new HDL standard.

6. Theory base: all wave-pipelining circuits are different in their 1-cycle logic, but other logic relating to the wave-pipelining parts are the same and classified into 3 categories that leads to 3 entities.

7. Example circuits: FFT-16; floating A*B --> C;

Weng

So what software handles the timing analysis and balances the delays???

If you are expecting the synthesis software to do the heavy lifting of timing analysis, what exactly do your libraries do? What are your three entities?

BTW, do you realize the synthesis software doesn't actually know the timing of an FPGA circuit??? Timing is determined as much by the routing as it is the logic elements. So it is up to the chip vendor's place and route tools to get that right. This would not be an easy task to accomplish.

And of course all of this ignores the fact that minimum delays are just as important as maximum delays in FPGA logic. It is hard to tell if you could ever get this to work across the three variables of timing, process, voltage and temperature. Every chip will vary. Each board with slightly different PS voltages will vary. Every operating temperature will vary. For a wave pipeline to work all of the inputs to the delay equation have to result in a very small window of delay variation.

How do you plan to control any of that?

Rick C.

Tesla referral code -++ https://ts.la/richard11209
Get 6 months of free supercharging -++

Rick,

Intel first finished its 8087 chip using the wave-pipelining technology. Nowadays every company has the technology. Based on my knowledge, even Chinese Huawei cellphone company uses the technology comfortably.

You are right that Xilinx and Altera also have the potential to control the technology. Nowadays any variations of temperatures, routine delays and voltages are well known and calculated.


The 8087 is not an FPGA. Nothing you have said addresses the fundamental limitations to using wave-pipelining in FPGAs. It doesn't matter if you can calculate the delay variation from PVT or routing. Knowing it isn't the problem, controlling it is. There is nothing the user can do about PVT so it is a variable that blurs the arrival time of the signal to the actual FF. When that blurring becomes wider than a clock cycle you have to slow the clock. Processing variations will likely be the largest contributor and there is nothing to be done about it until they start binning chips for a speed range rather than just maximums.

The other issue that has been pointed out to you is that in FPGAs there are typically an excess of FFs RIGHT NEXT to the LUTs. So if you save FFs by wave-pipelining you have done little if anything. Perhaps a small amount of power.

Rick C.

- Get 6 months of free supercharging
- Tesla referral code - https://ts.la/richard11209


Guest

Sun Dec 23, 2018 7:45 pm   



On Sunday, December 23, 2018 at 11:43:29 AM UTC-5, HT-Lab wrote:
Quote:
On 23/12/2018 06:33, gnuarm.deletethisbit_at_gmail.com wrote:
On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote:
Rick,
..

So what software handles the timing analysis and balances the delays???

If you are expecting the synthesis software to do the heavy lifting of timing analysis, what exactly do your libraries do? What are your three entities?

BTW, do you realize the synthesis software doesn't actually know the timing of an FPGA circuit???

To do a bit of nitpicking, they do (have to for timing optimisations)
and I am not talking about a wire-load model. High-end synthesis tool
offer what is called Physical Aware Synthesis (PAS). What they do is to
run an internal placer (or use the P&R vendors version) and use that to
estimate the timing to a surprising degree of accuracy. Apparently they
do not need to run the actual routing as this is not required for a good
estimate.


I'd love to know more about that. If they don't know the routing in the end design how can they know the timing? I don't know how you would "estimate" the timing. In particular, the timing required by wave-pipelining would be much more detailed than in regular design requiring limits on the minimum AND maximum delays of *each path*, not just logic.

I can't see how this would be possible, much less practical in any real world design other than regular structures like multipliers, etc.


Quote:
Timing is determined as much by the routing as it is the logic elements.

I would say that for modern FPGA's the routing is normally the timing
killer (on my designs routing delay >2x logic delay). I guess this is
the reason products like Plunify (no affiliation) are so successful.

So it is up to the chip vendor's place and route tools to get that right.. This would not be an easy task to accomplish.

And of course all of this ignores the fact that minimum delays are just as important as maximum delays in FPGA logic. It is hard to tell if you could ever get this to work across the three variables of timing, process, voltage and temperature. Every chip will vary. Each board with slightly different PS voltages will vary. Every operating temperature will vary. For a wave pipeline to work all of the inputs to the delay equation have to result in a very small window of delay variation.
How do you plan to control any of that?


Rick C.

+ Get 6 months of free supercharging
+ Tesla referral code - https://ts.la/richard11209

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