What is the most area efficient CRC method

Wed Feb 03, 2010 2:21 pm   

Hi,
I need to implement CRC detection in a Spartan3 Xilinx FPGA. My data strea
is coming in one byte at a time, but I do have about 8-10 clock cycle
between each byte (still tbd!).

If I want to save area, is it better to use a CRC that works byte per byt
or bit per bit?

Also, any idea where I could find code for the standard polynomials?

Thanks!
Diego

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Wed Feb 03, 2010 3:00 pm   

On Wed, 03 Feb 2010 07:21:13 -0600, dlopez wrote:


There is a great polynomial generator on the web,

http://www.easics.com/webtools/crctool

Wed Feb 03, 2010 4:13 pm   

"dlopez" <d_at_n_o_s_p_a_m.designgame.ca> writes:


Per bit as it is simply a shift register with xor gates at the
polynomial positions.


Here is a sample program to symbolically convert a serial form to a
parallel form:

http://tinyurl.com/ygvenaz

Petter
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Thu Feb 04, 2010 4:41 am   

On Feb 3, 10:13 am, Petter Gustad <newsmailco...@gustad.com> wrote:

To do a serial CRC calculation requires a state machine to control
it. A parallel CRC has to perform multiple xors for each bit using
extra logic compared to the bit serial version, the difference
depending on the size of the CRC. The question is which uses more
logic, a byte parallel CRC generator or the control logic for the
state machine. Depending on the CRC chosen, I bet it is close to a
wash, but the only way to know for sure is to build both and see.

Thu Feb 04, 2010 6:33 am   

In article <1e71b867-02c0-4702-973b-355411c39446_at_t21g2000vbo.googlegroups.com>,
rickman <gnuarm_at_gmail.com> writes:


The bit serial CRC has a simple structure. It can easily run
at a high clock rate.

The parallel CRC turns into an ugly cloud of XORs. The details
depend upon the polynomial and how many bits you are processing
in parallel. Expect it to turn into a good test case for the
placer and router.

If the OP doesn't have enough clocks to process things in
bit serial, it might work out better to do 2 bits in parallel
on each of 4 clocks. I think that needs 4 inputs worst case
so it fits in one layer of LUT. (I'm rusty on this, but years
ago I spent a lot of time in this area. I think I've made all
possible screwups while writing software to check things.
There are a lot of wrong possibilities when you consider big
endian vs little endian, shifting right or left or ...)

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Wed Feb 10, 2010 7:17 am   

There is an article in Jan '10 issue of CircuitCellar magazine ( page
40, http://www.scribd.com/doc/24890014/Circuit-Cellar-January-2010-TV
) that discusses different parallel CRC implementation methods.


Thanks,
Evgeni

Sat Feb 27, 2010 3:03 pm   

the the easiest and the least resource intensive. The architecture i
essentially a shift register with XOR gates inserted between some of th
flops. Like others have mentioned, web based CRC calculation tools can b
very useful when debugging the design.



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