what is incorrect about my usage of array with port entity?

Wed Feb 17, 2010 3:00 pm   

library ieee;
library work;
use ieee.std_logic_1164.all;

use ieee.numeric_std.all;


entity delay_line_interleaved is
generic(
numtaps : integer := 18;
wordlength_in : integer := 14;
coefflen : integer := 20
);
port(
-- INPUT PORTS --
clkin : in std_logic;
rst : in std_logic;
ena : in std_logic;
in_pddc : in std_logic_vector(wordlength_in-1 downto 0); --enough bit
here and other places to handle number of adds?
-- OUTPUT PORTS --
dv_out : out std_logic;
x_delay_line : out array (0 to coefflen-1) o
std_logic_vector(wordlength_in-1 downto 0)
);
end entity;



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Wed Feb 17, 2010 5:10 pm   

VHDL doesn't allow explicitly 2-dimensional arrays as entity ports.
Why?
Because!

You will have to define a 2-D type in a package, and use that instead.

BTW, "library work;" is redundant.

HTH!



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