What is a difference between an array of instance and genera

Sun Jul 18, 2010 8:02 pm   

Hello
What is a difference between an array of instance and generate for
loop?
Thank you

Sun Jul 18, 2010 8:02 pm   

On Sun, 18 Jul 2010 10:02:52 -0700 (PDT), "Yakovm3_at_gmail.com" wrote:


Generate loops are somewhat more flexible than instance arrays,
because instance arrays have very rigid rules about how the
ports of the instances should be connected (although those
rules do what's needed in almost all the common cases).

Generates allow you to put more than just the module instance
in each "iteration" of the loop. This can be very useful
when, for example, you need some glue logic associated with
each instance in the array.

But generate's flexibility comes at a price. The body of
a generate loop is a new, named scope. So the names of the
instances are rather complicated:

module M(...);
endmodule

module uses_many_M;
...
M [3:0] M_array (...); // creates instances
// M_array[0], M_array[1], ...
...
generate
genvar i;
for (i=0; i<=3; i++) begin: gen_inst
M M_gen(...); // instance gen_inst[0].M_gen, etc
end
endgenerate
...
endmodule

In Verilog-2005 the requirement to name the begin..end
block was dropped, but if you don't provide a name the
compiler will provide one for you, so you can't get
away from the extra level of scope.

For synthesis, where you never make dotted name
references, the extra level of scope probably doesn't
matter unless you're inspecting the post-synthesis
netlist. For simulation, though, the added complexity
can be tiresome if you want to make cross-module
reference into one of the generated module instances.
--
Jonathan Bromley

Thu Jul 22, 2010 11:53 pm   

On Jul 18, 10:02 am, "Yako...@gmail.com" <yako...@gmail.com> wrote:

Arrays can help out when you have multiple instances of an interfaces.
E.g. a multiport arbiter that has req and gnt. In this case you can
declare the interface as an array in the arbiter module. And then in
the top-level you could connect to individual interfaces from a
generate block.

/////
module top
#(parameter NUM_OF_PORTS = 4)
(
...
);

arb_if inst_arb_if [NUM_OF_PORTS-1:0]();

genvar i;
generate for (i=0;i<NUM_OF_PORTS;i+=1) begin : proc_blk
processor inst_processor (
.arb_if (inst_arb_if[i])
);
end
endgenerate

arbiter
#(.NUM_OF_PORTS(NUM_OF_PORTS) )
inst_arbiter (
.arb_if (inst_arb_if)
);

endmodule