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What does '->' mean in this code snippet?

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elektroda.net NewsGroups Forum Index - Verilog Language - What does '->' mean in this code snippet?

Robert Willy
Guest

Sat Dec 30, 2017 1:58 am   



Hi,

I find the '->' usage is rather new to me. What is it?


Thanks in advance.







casex({fmt, f_type})

PCI_EXP_MEM : begin
payload = 0;
TSK_3DW(fmt, f_type, _log_file_ptr, log_file);

if (log_file == RX_LOG)
-> rcvd_memrd;
end

PCI_EXP_IO : begin
payload = 0;
TSK_3DW(fmt, f_type, payload, _frame_store_idx, _log_file_ptr, log_file);

if (log_file == RX_LOG)
-> rcvd_iord;
end

john p
Guest

Sat Dec 30, 2017 3:45 am   



On Friday, December 29, 2017 at 3:58:48 PM UTC-8, Robert Willy wrote:
Quote:
Hi,

I find the '->' usage is rather new to me. What is it?


Thanks in advance.







casex({fmt, f_type})

PCI_EXP_MEM : begin
payload = 0;
TSK_3DW(fmt, f_type, _log_file_ptr, log_file);

if (log_file == RX_LOG)
-> rcvd_memrd;
end

PCI_EXP_IO : begin
payload = 0;
TSK_3DW(fmt, f_type, payload, _frame_store_idx, _log_file_ptr, log_file);

if (log_file == RX_LOG)
-> rcvd_iord;
end


It indicates triggering an event. This is not a synthesizable construct, it's used for tesbenches and behavioral models.

As I recall, you declare an event like:
event foo;
Then use it like
always @(foo)
// do something

Hope this helps

Gabor
Guest

Sat Dec 30, 2017 4:04 am   



On Friday, 12/29/2017 8:45 PM, john p wrote:
Quote:
On Friday, December 29, 2017 at 3:58:48 PM UTC-8, Robert Willy wrote:
Hi,

I find the '->' usage is rather new to me. What is it?


Thanks in advance.







casex({fmt, f_type})

PCI_EXP_MEM : begin
payload = 0;
TSK_3DW(fmt, f_type, _log_file_ptr, log_file);

if (log_file == RX_LOG)
-> rcvd_memrd;
end

PCI_EXP_IO : begin
payload = 0;
TSK_3DW(fmt, f_type, payload, _frame_store_idx, _log_file_ptr, log_file);

if (log_file == RX_LOG)
-> rcvd_iord;
end

It indicates triggering an event. This is not a synthesizable construct, it's used for tesbenches and behavioral models.

As I recall, you declare an event like:
event foo;
Then use it like
always @(foo)
// do something

Hope this helps


This is new to me, too. Is this in Verilog as well as SystemVerilog?

--
Gabor

unfrostedpoptart
Guest

Sun Dec 31, 2017 12:19 am   



On Friday, December 29, 2017 at 6:04:43 PM UTC-8, Gabor wrote:
Quote:
On Friday, 12/29/2017 8:45 PM, john p wrote:
On Friday, December 29, 2017 at 3:58:48 PM UTC-8, Robert Willy wrote:
Hi,

I find the '->' usage is rather new to me. What is it?
Thanks in advance.
casex({fmt, f_type})

PCI_EXP_MEM : begin
payload = 0;
TSK_3DW(fmt, f_type, _log_file_ptr, log_file);

if (log_file == RX_LOG)
-> rcvd_memrd;
end
It indicates triggering an event. This is not a synthesizable construct, it's used for tesbenches and behavioral models.

As I recall, you declare an event like:
event foo;
Then use it like
always @(foo)
// do something

Hope this helps
This is new to me, too. Is this in Verilog as well as SystemVerilog?


Yep - it's always been there. They're great for handshaking and other triggering since they aren't high or low - just inactive and active and have zero duration. Some waveform viewers show them as arrows pointing up since they're kind-of like an impulse (Dirac delta function) in electronics.

elektroda.net NewsGroups Forum Index - Verilog Language - What does '->' mean in this code snippet?

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