VHDL vs. verilog question

Wed Jul 28, 2010 8:13 pm   

I'm trying to create a phase frequency detector, like the one
in figure 1 of this article:

http://www.analog.com/library/analogDialogue/archives/33-07/phase3/

I believe the VHDL code would be something like this:

process(in_a, in_b, up, down)
begin
if up = '1' and down = '1' then
up <= '0';
down <= '0';
else
if rising_edge(in_a) then
up <= '1';
end if;
if rising_edge(in_b) then
down <= '1';
end if;
end if;
end process;

Now, what I *actually* want to do is to model this circuit in MyHDL: www.myhdl.org

MyHDL follows the verilog coding style (I understand a little bit of VHDL
but not verilog).

My question is: Is it possible to write the above code in a similar
way in verilog (or MyHDL)? Is it possible to have a 'process' or what
it's called in verilog that has two edge sensitive signals in the sensitivity list?

Hope you can understand my question and thanks,
Thomas

Thu Jul 29, 2010 12:20 am   

On 7/28/2010 3:36 PM, Andy wrote:

Why not? It's two D-flops with a 1 on the data input, clocked by two
separate clocks, with an asynch clear from the and of the two outputs.
You get some interesting dead band issues based on the routing delay of
that clear path, but you can certainly make it work.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Thu Jul 29, 2010 1:36 am   

This can be represented in two separate processes, one clocked by
in_a, and the other by in_b.

I hope you are not planning on synthesizing this to an FPGA.

Andy

Thu Jul 29, 2010 6:38 pm   

It is the race condition on the clear signal that would concern me in
an FPGA, making sure that the first flop is not cleared, thus removing
the clear signal, before the second flop is cleared. It could be made
to work reliably with a lot of fuss and analysis (assuming the FPGA
vendor provides minimum delay specifications on async clear, routing,
etc.) but it would not be a good idea for someone who needs basic help
in synthesis.

Andy

Fri Jul 30, 2010 2:35 pm   

Andy schrieb:

Ok, so what are the alternatives? The circuit from xapp028, which I found here?

http://www.eettaiwan.com/ARTICLES/2000JUN/2000JUN29_AMD_PL_AN572.PDF?SOURCES=DOWNLOAD

Fri Jul 30, 2010 2:36 pm   

Andy schrieb:

Ok, so the answer to my real question seems to be: a verilog process,
different from a VHDL process, can only have one edge-sensitive signal.

Correct?

Fri Jul 30, 2010 4:55 pm   

On Jul 30, 8:36 am, Thomas Heller <thel...@python.net> wrote:

No, I don't know what verilog will allow. I'm just pointing out that
you don't need it to handle dual-clocked processes to handle this
circuit.

Andy

Fri Jul 30, 2010 5:07 pm   

Andy schrieb:

And indeed, the circuit from xapp028 isn't recommended any more for newer
devices. Here is a thread where this is discussed:

http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/b42f882e2849011f/f89506f566d0568c#f89506f566d0568c



I'll think this idea over.


Thanks, Andy, for these tips. It seems that the AD9901 chip contains
a phase-frequency detector that could be implemented inside an fpga
without problems; however, I have to check if I can use it for my
application (I fear I cannot .


Thomas

Fri Jul 30, 2010 5:31 pm   

A circuit designed for relatively slow FPGA families from 10 years ago
may not work as well (or be as easily made to work well) in a modern,
very fast FPGA. Quite frankly, I like the original design better than
the xapp one.

What does this phase detector drive, an external filter and VCO, or an
internal synchronous NCO, or something else? Alternatives differ
widely based on the answer. Consider whether you need an asynchronous
phase detector, or whether a more synchronous design might work with
whatever it needs to control.

What the first design needs is a way to make sure the async clear does
not go away as soon as one of the registers is cleared. You could do
this with a third flop, set (clock in a '1') when the two flops are
both set, and cleared when both are cleared. Use the output of this
third flop to clear the first two. This may cause other problems
though with dead-band issues, meta-stability, etc.

However, I must also warn you: using combinatorial circuits (remember,
these are LUTs, not ANDs and ORs) to drive causal signals (clocks and
async resets) can be risky (glitchy), especially in cases where more
than one input to the LUT is changing at a time. The muxes in the LUTS
are very well balanced to minimize this, but "there ain't nothin'
perfect".

Generally speaking, the more synchronous the design, the fewer
problems getting it to work reliably (across different die, power
supply voltages, temperatures, aging, etc.).

Andy

Fri Jul 30, 2010 6:13 pm   

Andy Peters schrieb:


I know this very well, having designed digital circuits since 35 years
And not all clock signals have to go into the same flip-flop's clock input.

Part of the question in my original post was: How would the below VHDL code
look like in a single verilog process:

process(in_a, in_b, up, down)
begin
if up = '1' and down = '1' then
up <= '0';
down <= '0';
else
if rising_edge(in_a) then
up <= '1';
end if;
if rising_edge(in_b) then
down <= '1';
end if;
end if;
end process;



Thomas

Fri Jul 30, 2010 7:47 pm   

On Jul 30, 6:36 am, Thomas Heller <thel...@python.net> wrote:

No, both Verilog and VHDL allow processes to be sensitive to the edges
of any number of signals. Certainly for behavioral modeling this is
perfectly OK.

However, you have to realize that FPGA flip-flops are sensitive to the
edge of only one signal, so the synthesis tools will likely barf on
code that uses more than one signal's edge.

-a

Fri Jul 30, 2010 10:53 pm   

Many FPGA synthesis tools will allow more than one clock edge in a
process. They usually won't allow assignments to the same signal/
variable on more than one clock, but that is not being done in this
example.

Some FPGAs have DDR flops in the IOBs. Not sure whether any tools will
infer a DDR flop from a two clock process assigning the same var/sig
on both clocks.

Andy

Fri Jul 30, 2010 11:07 pm   

On Jul 30, 7:13 pm, Thomas Heller <thel...@python.net> wrote:

Interesting, isn't it? You ask a question about modeling
and everyone is immediately concerned about synthesis :-)

What you need is way to check, in an if statement, which
signal has just seen an event.

I'm not aware of a way to do this in Verilog, although of
course the proper forum to ask would be comp.lang.verilog.
(Who knows what can be found in the dark corners of the
standards...)

It cannot be done in MyHDL either, although it would certainly
be possible to support this, e.g. by a Signal.event attribute.
I would be reluctant to add this, because it would add
operations in the main simulation loop for an uncertain
value, given that the whole Verilog community can
perfectly live without it ... (not entirely sure about
that argument either though )

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com

Sat Jul 31, 2010 10:09 am   

On Fri, 30 Jul 2010 13:07:26 -0700 (PDT), Jan Decaluwe wrote:


Ah. Like "rising_edge(sig)" or "sig'event" or something
really silly like that? The kind of stuff that only
dumb software wonks, writing a bloated language like
VHDL, would think of? :-)


It's not wildly hard, but it needs care.

always @(sigA, sigB) begin
reg old_sigA, old_sigB;
if (sigA !== old_sigA) begin
// sigA has changed
end
if (sigB !== old_sigB) begin
// sigB has changed
end
old_sigA = sigA;
old_sigB = sigB;
end

Note that you must keep the "old" values IN THE
SAME SEQUENTIAL BLOCK as you used to do the test,
otherwise you're exposed to all manner of race
conditions. Tedious, because it means you must
replicate the "old-keeper" code in each place
you might need it.

Note, too, the use of !== for comparison.

The same code works fine for multi-bit signals
too, although of course you must be careful
to declare the "old_" variables to be the same
size as the signals of interest.

Needless to say, this is modelling code and
won't synthesise correctly!

SystemVerilog adds some alternative tricks for
doing similar things, with its event variables
and event .triggered property.

cheers
--
Jonathan Bromley

Sat Jul 31, 2010 8:35 pm   

Jan,

So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?

Andy