elektroda.net NewsGroups Forum Index - VHDL Language - VHDL vs. verilog question
Jan Decaluwe
Guest
Guest
Tue Aug 03, 2010 4:58 pm
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
Quote:
Jan,
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
Andy
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
Andy
With Jonathans's somewhat brute-force method I guess
Mm, perhaps I really should consider adding an .event
attribute, or doing it like in SystemVerilog if someone
can tell me how that is exactly ...
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
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Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Marcus Harnisch
Guest
Guest
Wed Aug 04, 2010 12:56 pm
Jan Decaluwe <jan_at_jandecaluwe.com> writes:
Quote:
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess
But why has nobody asked about the rationale for the requirement(?)
implementing the original function in one process? Nobody here
seriously believes that this would simulate faster?!
Regarding the DDR register above, just use two processes assigning to
the same register. As opposed to VHDL concurrent drivers, in Verilog
the last assignment wins. Should both clock edges occur
simultaneously, it is undefined which assignment is effective. I guess
that models the real world pretty well.
always @(posedge clk0, posedge reset) begin
if (reset)
q <= 0;
else
q <= d0;
end
always @(posedge clk1, posedge reset) begin
if (reset)
q <= 0;
else
q <= d1;
end
--
Marcus
note that "property" can also be used as syntactic sugar to reference
a property, breaking the clean design of verilog; [...]
(seen on http://www.veripool.com/verilog-mode_news.html)
Jan Decaluwe
Guest
Guest
Wed Aug 04, 2010 5:33 pm
On Aug 4, 1:56 pm, Marcus Harnisch <marcus.harni...@gmx.net> wrote:
Quote:
Jan Decaluwe <j...@jandecaluwe.com> writes:
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess :-)
But why has nobody asked about the rationale for the requirement(?)
implementing the original function in one process? Nobody here
seriously believes that this would simulate faster?!
Regarding the DDR register above, just use two processes assigning to
the same register. As opposed to VHDL concurrent drivers, in Verilog
the last assignment wins. Should both clock edges occur
simultaneously, it is undefined which assignment is effective. I guess
that models the real world pretty well.
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess :-)
But why has nobody asked about the rationale for the requirement(?)
implementing the original function in one process? Nobody here
seriously believes that this would simulate faster?!
Regarding the DDR register above, just use two processes assigning to
the same register. As opposed to VHDL concurrent drivers, in Verilog
the last assignment wins. Should both clock edges occur
simultaneously, it is undefined which assignment is effective. I guess
that models the real world pretty well.
I suspect the reason is that VHDL designers tend to care about
determinism. The fact that the real world is non-deterministic doesn't
imply that it's a good idea to make your simulations non-deterministic
also.
Jan
Andy
Guest
Guest
Wed Aug 04, 2010 5:48 pm
On Aug 4, 9:33 am, Jan Decaluwe <jandecal...@gmail.com> wrote:
Quote:
On Aug 4, 1:56 pm, Marcus Harnisch <marcus.harni...@gmx.net> wrote:
Jan Decaluwe <j...@jandecaluwe.com> writes:
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess :-)
But why has nobody asked about the rationale for the requirement(?)
implementing the original function in one process? Nobody here
seriously believes that this would simulate faster?!
Regarding the DDR register above, just use two processes assigning to
the same register. As opposed to VHDL concurrent drivers, in Verilog
the last assignment wins. Should both clock edges occur
simultaneously, it is undefined which assignment is effective. I guess
that models the real world pretty well.
I suspect the reason is that VHDL designers tend to care about
determinism. The fact that the real world is non-deterministic doesn't
imply that it's a good idea to make your simulations non-deterministic
also.
Jan- Hide quoted text -
- Show quoted text -
Jan Decaluwe <j...@jandecaluwe.com> writes:
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess :-)
But why has nobody asked about the rationale for the requirement(?)
implementing the original function in one process? Nobody here
seriously believes that this would simulate faster?!
Regarding the DDR register above, just use two processes assigning to
the same register. As opposed to VHDL concurrent drivers, in Verilog
the last assignment wins. Should both clock edges occur
simultaneously, it is undefined which assignment is effective. I guess
that models the real world pretty well.
I suspect the reason is that VHDL designers tend to care about
determinism. The fact that the real world is non-deterministic doesn't
imply that it's a good idea to make your simulations non-deterministic
also.
Jan- Hide quoted text -
- Show quoted text -
To add to that, I would want my model to tell me if it could not
determine what the modelled behavior (i.e. hardware) would/should do.
This could be via an assertion failure and/or by assigning the output
to 'X' if both clocks occurred at the same time. Maybe there's a way
to do that in verilog and/or myhdl?
Andy
Andy
Guest
Guest
Wed Aug 04, 2010 6:05 pm
On Aug 4, 6:56 am, Marcus Harnisch <marcus.harni...@gmx.net> wrote:
Quote:
Jan Decaluwe <j...@jandecaluwe.com> writes:
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess :-)
But why has nobody asked about the rationale for the requirement(?)
implementing the original function in one process? Nobody here
seriously believes that this would simulate faster?!
Regarding the DDR register above, just use two processes assigning to
the same register. As opposed to VHDL concurrent drivers, in Verilog
the last assignment wins. Should both clock edges occur
simultaneously, it is undefined which assignment is effective. I guess
that models the real world pretty well.
always @(posedge clk0, posedge reset) begin
if (reset)
q <= 0;
else
q <= d0;
end
always @(posedge clk1, posedge reset) begin
if (reset)
q <= 0;
else
q <= d1;
end
--
Marcus
note that "property" can also be used as syntactic sugar to reference
a property, breaking the clean design of verilog; [...]
(seen onhttp://www.veripool.com/verilog-mode_news.html)
On Jul 31, 7:35 pm, Andy <jonesa...@comcast.net> wrote:
So how is a DDR register (with two clocks and two data inputs) modeled
in verilog or myhdl?
With Jonathans's somewhat brute-force method I guess :-)
But why has nobody asked about the rationale for the requirement(?)
implementing the original function in one process? Nobody here
seriously believes that this would simulate faster?!
Regarding the DDR register above, just use two processes assigning to
the same register. As opposed to VHDL concurrent drivers, in Verilog
the last assignment wins. Should both clock edges occur
simultaneously, it is undefined which assignment is effective. I guess
that models the real world pretty well.
always @(posedge clk0, posedge reset) begin
if (reset)
q <= 0;
else
q <= d0;
end
always @(posedge clk1, posedge reset) begin
if (reset)
q <= 0;
else
q <= d1;
end
--
Marcus
note that "property" can also be used as syntactic sugar to reference
a property, breaking the clean design of verilog; [...]
(seen onhttp://www.veripool.com/verilog-mode_news.html)
Aha! I keep forgetting you can do that in verilog...
Reasons a single process is desired in vhdl include that it would
simulate faster, especially since it would allow using a variable
instead of a signal.
I suppose we all assume solutions in the forms we are most used to.
Thanks for keeping us honest.
Andy
Marcus Harnisch
Guest
Guest
Wed Aug 04, 2010 6:16 pm
Jan Decaluwe <jandecaluwe_at_gmail.com> writes:
Quote:
On Aug 4, 1:56 pm, Marcus Harnisch <marcus.harni...@gmx.net> wrote:
I suspect the reason is that VHDL designers tend to care about
determinism. The fact that the real world is non-deterministic doesn't
imply that it's a good idea to make your simulations non-deterministic
also.
I suspect the reason is that VHDL designers tend to care about
determinism. The fact that the real world is non-deterministic doesn't
imply that it's a good idea to make your simulations non-deterministic
also.
But this objection only applies to the solution for Andy's
problem. Thomas wants to drive individual signals which serve as their
own asynchronous resets. BTW, at which minimal phase difference do you
consider both edges simultaneous. Here is a solution which leaves q as
unknown if both clock edges occur in the same time step and try to
assign opposite values.
For most practical purposes in simulation[1] the code (using blocking
assignments) below should suffice:
always @(posedge clk0, posedge reset) begin
if (reset)
q = 0;
else begin
q = d0;
#0;
if (q != d0)
// the other block has been executed after this one in the
// same time step and assigned a different value
q = 1'bx;
end
end
always @(posedge clk1, posedge reset) begin
if (reset)
q = 0;
else begin
q = d1;
#0;
if (q != d1)
// the other block has been executed after this one in the
// same time step and assigned a different value
q = 1'bx;
end
end
But we are drifting away from the original request.
Footnotes:
[1] Since most DDR flops are implemented using special cells you
wouldn't want to synthesize this anyway.
--
Marcus
note that "property" can also be used as syntactic sugar to reference
a property, breaking the clean design of verilog; [...]
(seen on http://www.veripool.com/verilog-mode_news.html)
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