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Maurice
Guest
Sun Jan 10, 2010 4:11 pm
Hello:
I know very well VHDL, and nothing about Verilog. which is better and why?
thanks
Maurice
Jonathan Bromley
Guest
Sun Jan 10, 2010 7:22 pm
On Sun, 10 Jan 2010 17:11:27 +0200, "Maurice" wrote:
Quote:
I know very well VHDL, and nothing about Verilog. which is better and why?
are you trying to incite a riot?
--
Jonathan Bromley
Mike Treseler
Guest
Sun Jan 10, 2010 7:26 pm
Maurice wrote:
Quote:
I know very well VHDL, and nothing about Verilog. which is better and why?
Verilog has more built-in support for printing debug messages.
VHDL has more built-in support for advanced synthesis.
-- Mike Treseler
Maurice
Guest
Sun Jan 10, 2010 9:26 pm
"Jonathan Bromley" <jonathan.bromley_at_MYCOMPANY.com> wrote in message
news:7i3kk5do8v8ocs7v0p8emju2ccj09ajjs5_at_4ax.com...
Quote:
On Sun, 10 Jan 2010 17:11:27 +0200, "Maurice" wrote:
I know very well VHDL, and nothing about Verilog. which is better and why?
are you trying to incite a riot?
--
Jonathan Bromley
Not at all, why??
Simply, I don't know anything about verilog, I would just have an idea about
it, comparing with vhdl
Maurice
Maurice
Guest
Sun Jan 10, 2010 9:27 pm
"Mike Treseler" <mtreseler_at_gmail.com> wrote in message
news:7qukf1FbjsU1_at_mid.individual.net...
Quote:
Maurice wrote:
I know very well VHDL, and nothing about Verilog. which is better and
why?
Verilog has more built-in support for printing debug messages.
VHDL has more built-in support for advanced synthesis.
-- Mike Treseler
Thank you
Mike Treseler
Guest
Sun Jan 10, 2010 10:10 pm
Maurice wrote:
Quote:
"Jonathan Bromley" <jonathan.bromley_at_MYCOMPANY.com> wrote in message
are you trying to incite a riot?
Not at all, why??
Simply, I don't know anything about verilog, I would just have an idea about
it, comparing with vhdl
I am sure that Jonathan intended humor.
If you google this group on vhdl vs verilog
you will find many long and contentious treads.
-- Mike Treseler
Rob Gaddi
Guest
Mon Jan 11, 2010 6:05 pm
On Sun, 10 Jan 2010 17:11:27 +0200
"Maurice" <morisaab_at_yahoo.fr> wrote:
Quote:
Hello:
I know very well VHDL, and nothing about Verilog. which is better and
why?
thanks
Maurice
VHDL, because you already know it.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Petter Gustad
Guest
Mon Jan 11, 2010 6:22 pm
Mike Treseler <mtreseler_at_gmail.com> writes:
Quote:
VHDL has more built-in support for advanced synthesis.
What do you have in mind here?
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Mike Treseler
Guest
Mon Jan 11, 2010 6:28 pm
Petter Gustad wrote:
Quote:
Mike Treseler <mtreseler_at_gmail.com> writes:
VHDL has more built-in support for advanced synthesis.
What do you have in mind here?
Single process entities using no signals.
http://mysite.verizon.net/miketreseler/
Petter Gustad
Guest
Mon Jan 11, 2010 10:53 pm
Mike Treseler <mtreseler_at_gmail.com> writes:
Quote:
Petter Gustad wrote:
Mike Treseler <mtreseler_at_gmail.com> writes:
VHDL has more built-in support for advanced synthesis.
What do you have in mind here?
Single process entities using no signals.
Why is single process with no signals more advanced when it comes to
synthesis?
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Andy
Guest
Tue Jan 12, 2010 12:51 am
On Jan 10, 9:11 am, "Maurice" <moris...@yahoo.fr> wrote:
Quote:
Hello:
I know very well VHDL, and nothing about Verilog. which is better and why?
thanks
Maurice
If you need to do fixed or floating point arithmetic in hardware, VHDL
has it in spades over Verilog. This is just one example of the
inherent language capabilities (and not just syntactical sugar) of
VDHL that verlog lacks.
And as mentioned earlier, if you already know one, it is always better
than the one you don't know, unless you have a massive project ahead
and time to climb the learning curve.
Andy
Mike Treseler
Guest
Tue Jan 12, 2010 4:45 am
Petter Gustad wrote:
Quote:
Why is single process with no signals more advanced when it comes to
synthesis?
That is certainly a matter of opinion.
Structural vs procedural.
I prefer using variables, functions, and procedures
in a single box instead of modules upon modules.
-- Mike Treseler
Andy
Guest
Tue Jan 12, 2010 8:40 pm
On Jan 11, 9:45 pm, Mike Treseler <mtrese...@gmail.com> wrote:
Quote:
Petter Gustad wrote:
Why is single process with no signals more advanced when it comes to
synthesis?
That is certainly a matter of opinion.
Structural vs procedural.
I prefer using variables, functions, and procedures
in a single box instead of modules upon modules.
-- Mike Treseler
I also prefer the immediate update semantics of variables as opposed
to the postponed updates of signals in processes. "I stored this in
the sig up here, but it still has the old value down here later...".
Using variables often makes it easier to insert/remove clock cycles in
your behavioral description. Two references to the same variable can
be registered or combinatorial values independently. The synthesis
tool will do what it takes to create HW that mimics the clock cycle
behavior of your code, which now reads like SW code, without the
postponed values issues. It also makes more sense when using the
source level debugger.
These may or may not be "advantages" to other users.
Andy
David Bishop
Guest
Thu Jan 14, 2010 4:40 am
Maurice wrote:
Quote:
Hello:
I know very well VHDL, and nothing about Verilog. which is better and why?
I like VHDL mainly because I can do more with it than I can Verilog.
The argument boils down to this:
Verilog was written by a bunch of hardware guys who knew nothing about
software. We beat on it 'till you could do software with it.
VHDL was written by a bunch of software guys who knew nothing about
hardware. We beat on it 'till you could do hardware with it.
Petter Gustad
Guest
Sun Jan 17, 2010 9:00 pm
Mike Treseler <mtreseler_at_gmail.com> writes:
Quote:
Petter Gustad wrote:
Why is single process with no signals more advanced when it comes to
synthesis?
That is certainly a matter of opinion.
I see, so it's more a matter of taste.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
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