vhdl / verilog comparing

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Petter Gustad
Guest

Sun Jan 17, 2010 9:02 pm

Andy <jonesandy_at_comcast.net> writes:

Quote:

I also prefer the immediate update semantics of variables as opposed
to the postponed updates of signals in processes. "I stored this in
the sig up here, but it still has the old value down here later...".

Yuck. Synthesizable Ada comes to my mind. I guess I'm a little old
fashioned in this regard.

Petter
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Petter Gustad
Guest

Sun Jan 17, 2010 9:07 pm

David Bishop <dbishop_at_vhdl.org> writes:

Quote:

Verilog was written by a bunch of hardware guys who knew nothing about
software. We beat on it 'till you could do software with it.

Still I prefer SystemVerilog over VHDL for writing testbenches
using classes, constrained random generation, covergroups, queues,
assertions, and other software constructs.

Quote:

VHDL was written by a bunch of software guys who knew nothing about
hardware. We beat on it 'till you could do hardware with it.

Still I prefer VHDL over Verilog for writing DUT's.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Mike Treseler
Guest

Sun Jan 17, 2010 10:30 pm

Petter Gustad wrote:

Quote:

Why is single process with no signals more advanced when it comes to
synthesis?
That is certainly a matter of opinion.

I see, so it's more a matter of taste.

Yes. Bud Lite vs IPA Wink

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