VHDL problem

Fri Sep 30, 2011 3:24 pm   

I want to do something like this

signal slv : std_logic_vector(7 downto 0);
signal sl : std_logic;
signal res : std_logic;

res <= slv = x"01" and sl = '1';

But I get an error. I guess its something to do with them being differen
types. But I would of thought that the two terms would both resolve to 1 o
0 and then I could just "and" them.

Jon

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Fri Sep 30, 2011 3:45 pm   

Ok thanks, I thought there would be some kind of conversion functio
required.

Jon

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Fri Sep 30, 2011 5:36 pm   

On Sep 30, 11:24 am, "maxascent"
<maxascent_at_n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

No, (slv = x"01") resolves to type boolean as does (sl = '1'). I have
a function called to_std_logic that takes a boolean and returns a
std_logic for just such occasions. So then you have

res <= to_std_logic(slv = x"01" and sl = '1');

Kevin Jennings

Mon Oct 03, 2011 1:18 am   

On Sep 30, 11:45 am, "maxascent"
<maxascent_at_n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

KJ's reply hints at a pretty fundamental concept in VHDL: the language-
level logic is purposefully different from the digital logic used to
describe circuits (true/false vs. hi/lo/x/z/...).

For example, I would imagine KJ's "to_std_logic" function to include a
statement like:

output_logic <= '1' when (input_boolean = true) else '0';

Just something to keep in mind.

MB

Mon Oct 03, 2011 2:16 pm   

The trouble I am having is that I have been using Verilog for a number o
years but now need to use VHDL. As Verilog lets you do whatever you like,
have been finding VHDL quite hard going. But I am slowly beginning to ge
the hang of it.

Jon

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