VHDL newbie- stuck just weeks before project submission :(..

Sat Aug 07, 2010 8:16 pm   

Hello,

For my Masters project, I'm trying to implement a multiplier, and a
MAC where the outputs are calculated per clock cycle and stored in a
text file which can then be used for further processing.

However, both these designs are giving out partial products(I guess
they are partial products) at the output too, before they give the
final result..I've tried changing the codes, changing clock frequency
in testbench etc. but nothing seems to work...

Is there any way to implement a output_ready signal for multipliers/
adders?(I saw a few codes using shifter for rdy, but could not
understand the logic behind it)

I'm using the embedded Mult18X18 in Spartan 3..but do not want to use
the Core generator for MAC(which has a RDY signal) as the code has to
be kept portable.

Code for multiplier is--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Single_Mul is
Port ( Clk : in STD_LOGIC;
Mul1 : in STD_LOGIC_VECTOR (17 downto 0);
Mul2 : in STD_LOGIC_VECTOR(17 downto 0);
Mul_Res : out STD_LOGIC_VECTOR(35 downto 0));
end Single_Mul;

architecture Behavioral of Single_Mul is
Signal Prod : Signed( 35 downto
0):="000000000000000000000000000000000000";

begin
process(clk)is
begin

if rising_edge(Clk) then
Prod<=signed(Mul1)*signed(Mul2);
end if;
end process;

Prod_Process:Process(prod)
begin

Mul_Res<=STD_LOGIC_VECTOR(Prod);--here I was hoping this process is
--invoked only when the --clocked process above is complete...

end process;

end Behavioral;

Code for MAC--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_STD.all;

entity Mul_Adder is
Port ( MulA : in STD_LOGIC_VECTOR (17 downto 0);
MulB : in STD_LOGIC_VECTOR(17 downto 0);
Multi_Res : in STD_LOGIC_VECTOR(35 downto 0);
MulAdd_Res : out STD_LOGIC_VECTOR(35 downto 0);
Clk : in STD_LOGIC);
end Mul_Adder;

architecture Behavioral of Mul_Adder is
shared variable temp :SIGNED(35 downto
0);--:="000000000000000000000000000000000000";
Signal temp1:SIGNED(35 downto
0):="000000000000000000000000000000000000";

begin
Process(Clk) is
BEGIN

If rising_edge(Clk)
then
temp:=signed(MulA)*signed(MulB);
temp1<=signed(Multi_Res)+temp;
end if;

End Process;

MulAdd_Res_process: Process(temp1)
begin
MulAdd_Res<=STD_LOGIC_VECTOR(temp1);
end Process;

end Behavioral;

Am I doing anything wrong here? Any help in this direction would be
useful

Sun Aug 08, 2010 1:18 pm   

On 2010-08-07, Sheetal <sheetalgandhi333_at_gmail.com> wrote:

I couldn't see anything extremely weird in your code after a cursory
glance at it. Where did you observe this phenomenon?

Is it in RTL simulation?
Is it in post synthesis simulation?
Is it in post place and route simulation?
Is it in the real hardware?

regards
/Andreas

Mon Aug 09, 2010 11:55 am   

On Aug 7, 6:16 pm, Sheetal <sheetalgandhi...@gmail.com> wrote:

use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

Use either the IEEE NUMERIC_STD numeric_std OR the Synopsis
STD_LOGIC_UNSIGNED/STD_LOGIC_SIGNED, not both!
Your code is compatable with NUMERIC_STD, so stay with a good thing an
avoid the other libraries.

Regards
DG

Tue Aug 10, 2010 9:59 pm   

How is this different from:

architecture Behavioral of Mul_Adder is
-- no shared variables or signals needed
begin

Process(Clk) is
-- local (not shared) variable declaration for
-- combinatorial results from multiplier
variable temp :SIGNED(multi_res'range) := (others => '0');
BEGIN
If rising_edge(Clk) then
temp := signed(MulA) * signed(MulB);
MulAdd_Res <= STD_LOGIC_VECTOR(signed(Multi_Res) + temp;
end if;
End Process;

end Behavioral;

If this is giving you intermediate results on some clock cycles, it is
only because your inputs are intermediate values on some clock cycles.

In other words, the problem is not in this code, but in the code that
instantiates this entity/architecture.

Andy