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Sanity check on a weird bit of math and std_logic_unsigned

M. Norton

2 / 6

Wed Feb 01, 2012 7:48 pm JimLewis

Active-HDL/Xilinx Core FIFO Gen Sim Problem

roleohibachi

3 / 4

Tue Jan 31, 2012 9:28 pm MBodnar

Stimulus Counter (from Opto-Sensors)

Guest

3 / 7

Tue Jan 31, 2012 5:05 pm Thomas Stanka

Open Source VHDL Verification Methodology

HT-Lab

3 / 5

Mon Jan 30, 2012 11:49 am hssig

Spartan 6 MPMC - more ports?

Oliver Mattos

1 / 4

Thu Jan 26, 2012 8:55 am Christopher Head

GHDL and Tristate Busses

Rob Doyle

3 / 17

Wed Jan 11, 2012 2:47 am Brian Davis

Why isnt buffer used more often?

Tricky

8 / 23

Mon Jan 02, 2012 6:17 pm Paul Uiterlinden

concurrent signal assignment: order can matter?

Guest

5 / 13

Fri Dec 30, 2011 11:13 pm Michael Hermann

Version control for VHDL projects. [ Goto page: 1, 2 ]

Symon

21 / 157

Thu Dec 22, 2011 9:46 pm KJ

Can a vhdl function return a range?

mksuth

5 / 14

Tue Dec 20, 2011 11:21 am Tricky

A gray counter

fofo

1 / 14

Mon Dec 19, 2011 5:42 pm Gabor

convert boolean to std_logic

manolis kaliorakis

2 / 18

Sat Dec 17, 2011 7:58 pm manolis kaliorakis

psl assertion for dynamically created signal length

David Belohrad

1 / 14

Fri Dec 16, 2011 11:40 am HT-Lab

Getting rid of packages in VHDL code

Nicholas Kinar

4 / 19

Thu Dec 15, 2011 8:40 pm Nicholas Kinar

Converted signed 16 Bit to unsigned?

Steffen Koepf

1 / 16

Thu Dec 15, 2011 12:03 am Gabor

External name elaboration order

valtih1978

3 / 19

Tue Dec 13, 2011 4:34 am JimLewis

incremental generic association

sebs

3 / 17

Tue Dec 13, 2011 3:31 am JimLewis

SystemVerilog for verification

Rob Gaddi

9 / 27

Tue Dec 13, 2011 3:31 am JimLewis

Using Xilinx VHDL code with UNISIM on Altera toolset

Nicholas Kinar

9 / 25

Sun Dec 11, 2011 2:53 am Nicholas Kinar

How do you use serial port or any other bus

LM

7 / 15

Wed Nov 30, 2011 8:20 pm valtih1978

Function result not locally static in case expression

a s

8 / 14

Wed Nov 30, 2011 8:26 am Mike Treseler

PHDL a new HDL for PCB design

self

13 / 22

Wed Nov 23, 2011 6:56 pm Andy

Direct entity instantiation...

Brian Drummond

5 / 19

Mon Oct 31, 2011 3:01 pm Paul Uiterlinden

Local packages

hssig

8 / 31

Tue Oct 18, 2011 1:46 am JimLewis

Alias array / array of aliases

Colin Beighley

13 / 29

Sat Oct 15, 2011 8:51 am Alan Fitch

Is there delta=0 except at the beginning moment?

fl

2 / 35

Wed Oct 12, 2011 9:29 am Paul Uiterlinden

Testbench\Package Signal Visibility

Guest

5 / 44

Mon Oct 10, 2011 8:24 pm Mike Treseler

Cambridge U.K and the use of verilog

Jezmo

4 / 45

Tue Oct 04, 2011 10:21 pm Jezmo

Fast Counter [ Goto page: 1, 2 ]

Jessica Shaw

27 / 84

Sat Oct 01, 2011 4:52 pm John Kent

nonstandard use

churchy

2 / 37

Sat Sep 24, 2011 10:47 pm Jezmo

Would you like the alternative to Zero Ohm?

valtih1978

1 / 33

Sun Sep 11, 2011 3:06 pm hdlcohen@gmail.com

Is this an LRM thing, or Modelsim Bug?

Tricky

2 / 45

Wed Sep 07, 2011 10:38 am Martin Thompson

Configuring FPGA bulk chips

Insight Realm

2 / 49

Tue Sep 06, 2011 5:38 pm Nick Anghelidi

trouble connecting an out std_logic_vector port to aggregate

ihk

2 / 50

Fri Sep 02, 2011 11:38 pm Alan Fitch

Retrieving a signal parameter's name

Rob Gaddi

1 / 30

Fri Sep 02, 2011 5:24 pm Jonathan Bromley

regarding thesis

guranditta guranditta

1 / 35

Thu Sep 01, 2011 11:17 am Thomas Stanka

Clock Edge notation [ Goto page: 1 ... 103, 104, 105 ]

server

1574 / 22072

Thu Aug 25, 2011 12:56 pm Paul Uiterlinden

How do you introduce delays into 3-state (bi-dir) lines?

valtih1978

11 / 71

Tue Aug 16, 2011 5:09 pm valtih1978

Should VHDL allow Unicode identifiers and comments

Martin Thompson

10 / 65

Mon Aug 15, 2011 1:20 pm Anssi Saari

VHDL and System Verilog Assertions

thunder

1 / 41

Sun Aug 14, 2011 7:42 pm Jonathan Bromley

PSL book suggestions

thunder

2 / 53

Wed Aug 10, 2011 12:54 pm Matthias Alles

automating bringing of signals in hierarchical VHDL model to

fearg

10 / 62

Mon Aug 08, 2011 10:37 am Hendrik Eeckhaut

Monitoring inout signal transactions

valtih1978

1 / 45

Sat Jul 30, 2011 5:49 pm Guest

Is Partial Record Assignment Possible? [ Goto page: 1, 2 ]

Sudoer

16 / 152

Sat Jul 30, 2011 2:01 pm Jonathan Bromley

Exponential code in VHDL

Zaid Al-Hilli

5 / 68

Fri Jul 29, 2011 12:41 pm Zaid Al-Hilli

Assertions

thunder

3 / 48

Thu Jul 28, 2011 11:10 pm JimLewis

Design Built-in Self Test

abhishekshishodia

1 / 50

Sat Jul 23, 2011 7:05 pm KJ

Conditional declarations

Colin Beighley

5 / 46

Thu Jul 21, 2011 6:40 pm KJ

Attribute that shows if signal is clocked or not?

Colin Beighley

2 / 47

Thu Jul 21, 2011 5:37 pm Gabor

1to8 Demux code, can you look plz

majmoat_ensan

6 / 58

Thu Jul 21, 2011 2:31 am KJ

Goto page 1, 2, 3 ... 153, 154, 155  Next