maxascent
Guest
Wed Oct 05, 2011 1:35 pm
I have a memory that output a 64-bit slv. I have another module that has
record type with a data 64-bit slv input. I want to connect the tw
together. If I do this I get x. If I disconnect them the mem outputs what
expect. I can also connect a constant to the record and see that value. No
sure why I cant connect the two as I get no errors in modelsim.
TIA
J
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RCIngham
Guest
Thu Oct 06, 2011 8:00 am
Quote:
I have a memory that output a 64-bit slv. I have another module that ha
a
record type with a data 64-bit slv input. I want to connect the two
together. If I do this I get x. If I disconnect them the mem outputs wha
I
expect. I can also connect a constant to the record and see that value
Not
sure why I cant connect the two as I get no errors in modelsim.
Which tool is giving the problem?
Some synthesizers misinterpret your intentions unless you assign all of
signal in one concurrent assignment statement (that is, not in an explici
process).
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maxascent
Guest
Thu Oct 06, 2011 10:36 am
Thanks for the help. I actually had something else driving the signal.
J
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Thomas Stanka
Guest
Thu Oct 06, 2011 11:58 am
On 5 Okt., 15:35, "maxascent"
<maxascent_at_n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
Quote:
I have a memory that output a 64-bit slv. I have another module that has a
record type with a data 64-bit slv input. I want to connect the two
together. If I do this I get x. If I disconnect them the mem outputs what I
expect. I can also connect a constant to the record and see that value. Not
sure why I cant connect the two as I get no errors in modelsim.
X means you have 2 or more active driver on a signal driving different
values. Replace the std_logic_vector by std_ulogic_vector to detect in
compile time your problem.
Modelsim can't throw error, as your code is legal vhdl according to
lrm (but most likely useless/not what you like to get) and modelsim
simulates it correct.
bye Thomas
