VHDL and Sin

On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:

See the other responses.

I love the subject line.  Sin in VHDL, repent in Verilog?
--
Jonathan Bromley

hello all guys
I really need help to write a behavioral and RTL for:

e^sin(x) with |x| < 2

any help is appreciate thanks!

On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:

See the other responses.

I love the subject line.  Sin in VHDL, repent in Verilog?
--
Jonathan Bromley

dyadic sin()

On Mon, 7 Feb 2011 10:39:38 -0800 (PST), Andy wrote:
dyadic sin()

That's co-sin, right?

Jonathan Bromley

On Feb 3, 3:39 pm, Jonathan Bromley<s...@oxfordbromley.plus.com
wrote:
On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:

See the other responses.

I love the subject line. Sin in VHDL, repent in Verilog?
--
Jonathan Bromley

Well, there's original sin(), concurrent sin(), sequential (serial?)
sin(), procedural sin(), functional sin()

Let's not forget monadic err... unary sin() and dyadic sin().

Or just "Go Forth and sin() no more."

Andy

What resolution/performance do you need?

I'd start with some kind of ROM as a lookup table. To do better than that you'll need to do lots of maths to come up with an iterative algorithm that can come up with the exact result using only basic functions (* + -).

Il 07/02/2011 19:39, Andy ha scritto:



On Feb 3, 3:39 pm, Jonathan Bromley<s...@oxfordbromley.plus.com
wrote:
On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:

See the other responses.

I love the subject line.  Sin in VHDL, repent in Verilog?
--
Jonathan Bromley

Well, there's original sin(), concurrent sin(), sequential (serial?)
sin(), procedural sin(), functional sin()

Let's not forget monadic err... unary sin() and dyadic sin().

Or just "Go Forth and sin() no more."

Andy

I need to write an entity  for the approximate calculation of e^sin (x)
where x is a number representation in fixed point 2's complement, and |
x | <3.14 / 2.

my entity will be like this:

  exp_sin_x entity is
  port (x: in signed (15 downto 0), y: out signed (15 downto 0),
  clk: in std_ulogic)
  end entity;

  where the type is defined in the package signed IEEE / numeric_std, x
must be interpreted as a fixed point number format Q3.13 (i.e. x between
-4 and +4) and y as a fixed point number format with Q3.13 (then y lies
between -4 and +4)), clk is a clock signal to synchronize operations.

First I need a behavioral model and test it with a suitable test-bench.
Then I have to write a synthesizable RTL model is tested by comparing
the behavioral model.

I can approximate both the behavioral and structural model with:

  e ^ sin (x) with the polynomial P (x) = 1 + x + x ^ 2 / 2! - 3 / 4! x
^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6

(in the structural relationship, the coefficients are processed in fixed
point and the polynomial is calculated using fixed-point operations).

thanks again in advance

Am 03.02.2011 18:20, schrieb Oliver Mattos:
What resolution/performance do you need?

I'd start with some kind of ROM as a lookup table. To do better than
that you'll need to do lots of maths to come up with an iterative
algorithm that can come up with the exact result using only basic
functions (* + -).


I just have confessed my sin at opencores.org under arith/sincos.
If you can afford the block ram/rom you can use that as a starter.
Filling the table is in a function and is done in Pascal/C style
with floats.

On Feb 8, 10:20 am, tommy<pherak_tele...@alice.it> wrote:
Il 07/02/2011 19:39, Andy ha scritto:



On Feb 3, 3:39 pm, Jonathan Bromley<s...@oxfordbromley.plus.com
wrote:
On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:

See the other responses.

I love the subject line. Sin in VHDL, repent in Verilog?
--
Jonathan Bromley

Well, there's original sin(), concurrent sin(), sequential (serial?)
sin(), procedural sin(), functional sin()

Let's not forget monadic err... unary sin() and dyadic sin().

Or just "Go Forth and sin() no more."

Andy

I need to write an entity for the approximate calculation of e^sin (x)
where x is a number representation in fixed point 2's complement, and |
x |<3.14 / 2.

my entity will be like this:

exp_sin_x entity is
port (x: in signed (15 downto 0), y: out signed (15 downto 0),
clk: in std_ulogic)
end entity;

where the type is defined in the package signed IEEE / numeric_std, x
must be interpreted as a fixed point number format Q3.13 (i.e. x between
-4 and +4) and y as a fixed point number format with Q3.13 (then y lies
between -4 and +4)), clk is a clock signal to synchronize operations.

First I need a behavioral model and test it with a suitable test-bench.
Then I have to write a synthesizable RTL model is tested by comparing
the behavioral model.

I can approximate both the behavioral and structural model with:

e ^ sin (x) with the polynomial P (x) = 1 + x + x ^ 2 / 2! - 3 / 4! x
^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6

(in the structural relationship, the coefficients are processed in fixed
point and the polynomial is calculated using fixed-point operations).

thanks again in advance

First of all, why not look into the new IEEE fixed point package. For
VHDL '93 compatible version, see here: http://www.vhdl.org/fphdl/

Then you can do nice things like:

port (x: in sfixed (2 downto -13), y: out sfixed(2 downto -13) etc

So the bit numbers represent the real powers of 2 in the fixed point
numbers.

Then for a behavioural model, you can do this:

use ieee.math_real.all;
...
port (clk : in std_logic;
x: in sfixed (2 downto -13);
y: out sfixed(2 downto -13));
....
process
variable x_rl : real;
variable y_rl : real;
begin
wait until rising_edge(clk);
x_rl := to_real(x);
y_rl := math_e ** sin(x_rl);
y<= to_sfixed(y_rl, y'high, y'low);
end process;

This wont be synthesisable, but it is a nice simple behavioural model.
For a synthesisable implementation, a look up table is usually the
best approach, but at 16 bits thats a fair chunk of memory!