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Adam Wysocki
Guest

Thu Mar 08, 2018 2:45 pm   



Hi,

I started learning VHDL from the book "The Designer's Guide To VHDL"
(third edition) and I'm trying to make my first steps in it.

One of the exercises at the end of the first chapter asks to write an
entity declaration and a behavioral architecture body of a simple
multiplexer. Two inputs ('a' and 'b'), one selection input ('sel') and one
output, 'z', becoming 'a' if sel is 0, or 'b' if sel is 1.

I wrote the following code:

#v+
entity mux2 is
port (a, b, sel: in bit; z: out bit);
end entity mux2;

architecture mux2_behav of mux2 is begin
mux2: process is begin
if sel then
z <= b after 5ns;
else
z <= a after 5ns;
end if;
end process mux2;
end architecture mux2_behav;
#v-

(without test bench yet) and now I wanted to simulate it (I'm not sure if
it's possible without writing a test bench, but at least I want to have a
semantically correct architecture body).

Debian's apt-cache finds two simulators:

fauhdlc - experimental VHDL compiler and interpreter
freehdl - VHDL simulator for Linux

Unfortunately, gvhdl (freehdl's frontend) says that:

#v+
$ gvhdl ch1-10.vhdl
gvhdl: FreeHDL root path is '/usr'.
gvhdl: executing '/usr/bin/freehdl-v2cc -m ch1-10._main_.cc -L
/usr/share/freehdl/lib -o ch1-10.cc ch1-10.vhdl'
ch1-10.vhdl: in mux2(mux2_behav):
ch1-10.vhdl:7: sel does not match required type BOOLEAN, its type could be:
/usr/share/freehdl/lib/std/standard.vhdl:6: BIT
v2cc: ch1-10.vhdl: 1 errors
gvhdl: Compilation failed!
Died at /usr/bin/gvhdl line 211.
#v-

fauhdl doesn't recognize '5ns' symbol:

#v+
$ fauhdlc ch1-10.vhdl
ERROR> ch1-10.vhdl:8: Symbol '5ns' undefined.
ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined.
#v-

and after commenting it out says something similar to gvhdl:

#v+
$ fauhdlc ch1-10.vhdl
ERROR> ch1-10.vhdl:7: Type error for <sel>.
#v-

I understand that the statement "if sel then" is invalid for 'sel' being
a bit type, and not a boolean type.

This leads to my questions:

1. What am I doing wrong? Is it illegal to compare bits this way, or is it
legal only since a certain VHDL language version? The book says that it's
legal, but examples from the book fail with similar messages.

2. I don't know the VHDL version simulated by these two simulators, and if
they support VHDL-2008 or not. I read that comments /* ... */ are illegal
in VHDL versions prior to 2008, so I tried them in these simulators and
they complained, so I guess they support an older VHDL version.

I don't see any option to switch them to the 2008 version.

3. What simulators do you use or recommend? I prefer Linux ones (it would
be much easier for me), but if there are no reasonable ones, I can use
Windows ones as well. I want them only to test and simulate my code
snippets during learning. My final goal is to be able to make models
suitable for synthesis and upload into CPLD and FPGA devices.

Thank you!

--
[ Adam Wysocki :: Warsaw, Poland ]
[ Email: a_at_b a=grp b=chmurka.net ]
[ Web: http://www.chmurka.net/ ]

john
Guest

Thu Mar 08, 2018 6:45 pm   



In article <p7rbq7$bv3$1_at_node2.news.atman.pl>, gof_at_somewhere.invalid
says...
Quote:
3. What simulators do you use or recommend? I prefer Linux ones (it would
be much easier for me), but if there are no reasonable ones, I can use
Windows ones as well. I want them only to test and simulate my code
snippets during learning. My final goal is to be able to make models
suitable for synthesis and upload into CPLD and FPGA devices.

Thank you!


Hi Adam

I recently started learning VHDL myself - I bought a couple of top end
books and found them not to be good to learn from.

The example you are doing seems a popular one - take a look around
the net - I have an adder here I built starting from a similar example.

If you are doing this as serious as it sounds I'd recommend you go get
the Xilinx webpack release of Vivado.(Free to use but FPGA chip limited)
The limitations are mostly irrelevant when learning and can be ignored.
Its a mostly full toolchain with tons of documentation.
Dont be put off though - just work with your RTL files to start.
Then play with the provided IP when you are ready.
You get some example projects to load and play with too so you can
see how it all works right through the process. I find doing that helps to learn
even when I dont really understand much as I step though initially.

It runs identical on windows and linux (I have it on Centos-7 at the moment.)
I think ir runs on Suse and of course red-hat and probably any other spin offs
(scientific would probably work fine too.
You dont need a massive system to run it but I do recommend more that 4GB
ram (Some stuff will run in that but you can have a problem sometimes)
The application isnt all that power hungry.

As you can see - I'm a bit of a fan after using it a short while(but I did have
probelms with windows at first so I'd say stick with linux)
The forum is quite active and helpful too.

--

john

=========================
http://johntech.co.uk
=========================

Rob Gaddi
Guest

Thu Mar 08, 2018 7:45 pm   



On 03/08/2018 04:54 AM, Adam Wysocki wrote:

Quote:
[snip]

#v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:8: Symbol '5ns'
undefined. ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined. #v-

5 ns. The space matters.


Quote:
and after commenting it out says something similar to gvhdl:

#v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:7: Type error for
sel>. #v-

I understand that the statement "if sel then" is invalid for 'sel'
being a bit type, and not a boolean type.

This leads to my questions:

1. What am I doing wrong? Is it illegal to compare bits this way, or
is it legal only since a certain VHDL language version? The book says
that it's legal, but examples from the book fail with similar
messages.

2. I don't know the VHDL version simulated by these two simulators,
and if they support VHDL-2008 or not. I read that comments /* ... */
are illegal in VHDL versions prior to 2008, so I tried them in these
simulators and they complained, so I guess they support an older VHDL
version.

I don't see any option to switch them to the 2008 version.

That's only supported in VHDL-2008, earlier you have to use if sel = '1'
then. For GHDL you can run ghdl --options-help to be told that if you
want to use VHDL-2008 you need to compile (analyze) using the --std=08
argument. If you're going to use GHDL, for projects of any kind of size
(like 3 files). I strongly recommend setting up a Makefile or using VUnit.

Quote:
3. What simulators do you use or recommend? I prefer Linux ones (it
would be much easier for me), but if there are no reasonable ones, I
can use Windows ones as well. I want them only to test and simulate
my code snippets during learning. My final goal is to be able to make
models suitable for synthesis and upload into CPLD and FPGA devices.

Thank you!

The price is certainly right on GHDL, and Tristan works crazy hard on
it. As such it's actually got some of the most rigorous 2008 support
out there. I use it at home, and it definitely gets the job done. It
also definitely teaches you about rigor and the importance of
self-checking testbenches, since the integration with gtkwave for
actually graphically poking about is a pain. GHDL you will quickly find
you want your designs to be right the first time rather than having to
go spelunking. And that's not a bad thing. But it's a pain. You're
learning to drive on a high-performance vehicle with a hair-trigger
clutch, and you probably want a Toyota instead.

Professionally I use ModelSim DE, which is the sort of decision you can
make when it's the company footing the bill rather than your own pocket.
It makes life easy.

For what you're doing, you can probably get away with the free
simulators provided by whichever FPGA you decide you want to target
first. Xilinx's has a proprietary thing and Altera and Microsemi both
provide Modelsim (and I think Lattice as well); they all work on Linux.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

Adam Wysocki
Guest

Mon Mar 12, 2018 10:45 am   



Rob Gaddi <rgaddi_at_highlandtechnology.invalid> wrote:

Quote:
#v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:8: Symbol '5ns'
undefined. ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined. #v-

5 ns. The space matters.


Thanks.

Quote:
I don't see any option to switch them to the 2008 version.

That's only supported in VHDL-2008, earlier you have to use if sel = '1'
then. For GHDL you can run ghdl --options-help to be told that if you
want to use VHDL-2008 you need to compile (analyze) using the --std=08
argument. If you're going to use GHDL, for projects of any kind of size
(like 3 files). I strongly recommend setting up a Makefile or using VUnit.


Thanks, I tried ghdl... but I got stuck at trying to run my test bench:

#v+
entity test_bench is
end entity test_bench;

architecture test_mux2 of test_bench is
signal a, b, sel, z: bit;
begin
dut: entity work.mux2(mux2_behav)
port map (a, b, sel, z);
stimulus: process is begin
report "test start";

a <= '0';
b <= '1';
sel <= '0';
wait for 20 ns;
assert z = '0';

sel <= '1';
wait for 20 ns;
assert z = '1';

a <= '1';
b <= '0';
sel <= '0';
wait for 20 ns;
assert z = '1';

sel <= '1';
wait for 20 ns;
assert z = '0';

report "test end";
wait;
end process stimulus;
end architecture test_mux2;
#v-

ghdl -c --std=08 ch1-10.vhdl -r test_bench

This command got stuck 100% CPU usage and didn't print anything. After
giving more options for verbosity:

ghdl -c --std=08 ch1-10.vhdl -r test_bench --assert-level=note \
--stop-time=10ms --trace-signals --disp-time --trace-processes --stats \
--disp-order --disp-sources --disp-sig-types --disp-signals-map \
--disp-signals-table --checks --activity=all

it printed some diagnostic info, but still I can't find the 'z' signal
there...

#v+
..test_bench(test_mux2).a: 000000000281F380 net: -2 +A
..test_bench(test_mux2).b: 000000000281F270 net: -2 +A
..test_bench(test_mux2).sel: 000000000281F160 net: -2 +A
..test_bench(test_mux2).z: 000000000281F050 net: -1 +A
..test_bench(test_mux2).dut_at_mux2(mux2_behav).a: 000000000281F380 net: -2 +A
..test_bench(test_mux2).dut_at_mux2(mux2_behav).b: 000000000281F270 net: -2 +A
..test_bench(test_mux2).dut_at_mux2(mux2_behav).sel: 000000000281F160 net: -2 +A
..test_bench(test_mux2).dut_at_mux2(mux2_behav).z: 000000000281F050 net: -1 +A
0: 000000000281F380 +A net: -2 smode: signal #prt: 0 #drv: 1
1: 000000000281F270 +A net: -2 smode: signal #prt: 0 #drv: 1
2: 000000000281F160 +A net: -2 smode: signal #prt: 0 #drv: 1
3: 000000000281F050 +A net: -1 smode: signal #prt: 0 #drv: 1
1: end
run process .test_bench(test_mux2).dut_at_mux2(mux2_behav).mux2 [00000000027B62A0]
#v-

I guess it never runs the "stimulus" process, only the "dut" process...
I feel I'm still missing the big picture here.

Quote:
You're learning to drive on a high-performance vehicle with a
hair-trigger clutch, and you probably want a Toyota instead.


You mean VHDL? Or using ghdl?

Quote:
For what you're doing, you can probably get away with the free
simulators provided by whichever FPGA you decide you want to target
first.


I was thinking about Lattice's CPLD LC4064 (ispMACH), because it's
affordable and has enough I/O pins to not feel too limited...

Quote:
Xilinx's has a proprietary thing and Altera and Microsemi both provide
Modelsim (and I think Lattice as well); they all work on Linux.


Thanks, I'll take a look.

--
[ Adam Wysocki :: Warsaw, Poland ]
[ Email: a_at_b a=grp b=chmurka.net ]
[ Web: http://www.chmurka.net/ ]

Charles Bailey
Guest

Mon Mar 12, 2018 9:45 pm   



On 2018-03-08 06:54, Adam Wysocki wrote:
Quote:
mux2: process is begin
if sel then
z <= b after 5ns;
else
z <= a after 5ns;
end if;
end process mux2;
Your mux2 process needs a sensitivity list.


mux2: process(a, b, sel) is begin
if sel='1' then
z <= b after 5 ns;
else
z <= a after 5 ns;
end if;
end process mux2;

Or, you could just code it in one line like this:
z <= (a and not sel) or (b and sel) after 5 ns;


Charles Bailey

Paul Urbanus
Guest

Tue Apr 10, 2018 8:45 pm   



On 3/8/2018 6:54 AM, Adam Wysocki wrote:
Quote:
Hi,

I started learning VHDL from the book "The Designer's Guide To VHDL"
(third edition) and I'm trying to make my first steps in it.


<snipped>

Quote:

3. What simulators do you use or recommend? I prefer Linux ones (it would
be much easier for me), but if there are no reasonable ones, I can use
Windows ones as well. I want them only to test and simulate my code
snippets during learning. My final goal is to be able to make models
suitable for synthesis and upload into CPLD and FPGA devices.

Thank you!


For quick, small, things like this you can try
https://www.edaplayground.com/

This site is always up, but unfortunately the above site is down for
maintenance at the time of posting.

You have access to open source simulators (ghdl,...) as well as
commercial offerings (Aldec). There is a crude waveform viewer.
Hierarchical designs are supported. There are also tutorials.

I really like it for just playing around and trying things.

https://www.youtube.com/user/edaplayground

DISCLAIMER: I have no affiliation with EDA Playground. I just like it,
find it useful, and thought it might meet your needs.

Anssi Saari
Guest

Tue Nov 20, 2018 9:45 am   



gof_at_somewhere.invalid (Adam Wysocki) writes:

> fauhdl doesn't recognize '5ns' symbol:

Usually the time unit is specified separately from the value, so 5 ns
instead of 5ns.

Quote:
1. What am I doing wrong? Is it illegal to compare bits this way, or is it
legal only since a certain VHDL language version? The book says that it's
legal, but examples from the book fail with similar messages.


AFAIK, VHDL 2008 is needed for this kind of comparison.

Quote:
3. What simulators do you use or recommend? I prefer Linux ones (it would
be much easier for me), but if there are no reasonable ones, I can use
Windows ones as well. I want them only to test and simulate my code
snippets during learning. My final goal is to be able to make models
suitable for synthesis and upload into CPLD and FPGA devices.


I use Modelsim and Questa for work. Some FPGA vendors (at least Intel)
provide a free, "starter edition" of Modelsim for free. Which is usually
some versions behind and slows down if your design gets larger than some
limit. Great for small designs though.

Of the free simulators I've tried GHDL very briefly in Debian Linux some
time ago. GHDL is currently not in the package repositories so I built
from source which was somewhat complicated. And took up a surprising
amount of space I needed for other stuff so I deleted it. Also I have no
good idea on how well it supports VHDL 2008, support is described as
"partial" in the readme (https://github.com/ghdl/ghdl).

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