johnp
Guest
Thu Aug 11, 2011 12:53 am
We need to code some modules in both VHDL and Verilog and would like
to use a parameter/generic
to control inferring sync or async resets. Is there a clean way to
code this that is similar in both
VHDL and Verilog?
For example, we could try to use `define in Verilog, but this won't
port well to VHDL. I don't see how
wen can use generate statements in Verilog to do this nicely, either.
Any thoughts?
Thanks!
John Providenza
KJ
Guest
Thu Aug 11, 2011 4:02 am
On Aug 10, 6:53 pm, johnp <jprovide...@yahoo.com> wrote:
Quote:
We need to code some modules in both VHDL and Verilog and would like
to use a parameter/generic
to control inferring sync or async resets. Is there a clean way to
code this that is similar in both
VHDL and Verilog?
For example, we could try to use `define in Verilog, but this won't
port well to VHDL. I don't see how
wen can use generate statements in Verilog to do this nicely, either.
Any thoughts?
Thanks!
John Providenza
In VHDL, you could do have an entity generic control whether the async
reset logic gets called or not as shown below. The 'Do reset stuff'
can be implemeted as a procedure that gets invoked in the two places.
That way there is no need to copy/paste the reset actions into the two
places in the code.
process(Clock, Reset)
begin
if rising_edge(Clock) then
if (Reset = '1') and not(DO_ASYNC_RESET) then
-- Do reset stuff here
else
...
end if;
end if;
if (Reset = '1') and DO_ASYNC_RESET then
-- Do reset stuff here
end if;
end process;
Kevin Jennings
