Verilog to state diagram

Mon Jan 24, 2011 8:42 am   

I wonder if there is any software to generate a state
diagram from a verilog implementation of a state machine.

Presumably one would be more readable with a small number
of states, and one might have to be careful how one codes
the state machine such that it was properly recognized,
but it would seem to be useful. (Especially for debugging
failing state machines.)

-- glen

Mon Jan 24, 2011 9:47 pm   

On Mon, 24 Jan 2011 06:42:12 +0000 (UTC), glen herrmannsfeldt wrote:


All the FPGA synthesis tools I know of (Quartus, XST,
HDL Designer, Synplify) can do this. State diagram is
offered as a graphical view, as are schematics. And of
course some of those tools allow you to capture parts
of your design by graphical FSM entry, and mix them
with HDL pieces.

I've never tried to do it in the big-$$$ ASIC tools,
but they all have good schematic viewers so I guess
they probably have FSM visualisers too.


Breakpoints and single-stepping are just as good,
in my experience. Bubble charts are just exactly
what you want for some problems, I agree. But I've
written good (in the sense of concise, clear, effective)
state machine code that was rendered by the synthesis
tool as a picture of several kittens playing with
a ball of string.

However, as noted here many times, there are valid
and sensible things you can do in HDL state-machine
code that are implausibly hard to represent on a state
chart. That's the main reason I rarely bother with
the diagrams these days.

A good recent example of something for which I really
valued the FSM diagram (pencil and paper, in my case):
a JTAG interface, where the standard defines things
in terms of progress around a very conventional state
machine with few, simple branches.

Jonathan Bromley