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qq
Guest

Wed Jan 31, 2018 5:11 am   



Why am I getting "./functions.vh:44: syntax error" for https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/functions.vh#L44 ?

My testbench file is as followed:


`timescale 1ns/1ns
`include "functions.vh"

module async_fifo_fwft_tb;

parameter C_WIDTH = 32; // Data bus width
parameter C_DEPTH = 1024; // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH);
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH);
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1);

reg RD_CLK; // Read clock
reg RD_RST; // Read synchronous reset
reg WR_CLK; // Write clock
reg WR_RST; // Write synchronous reset
wire [C_WIDTH-1:0] WR_DATA; // Write data input (WR_CLK)
reg WR_EN; // Write enable, high active (WR_CLK)
wire [C_WIDTH-1:0] RD_DATA; // Read data output (RD_CLK)
reg RD_EN; // Read enable, high active (RD_CLK)
reg WR_FULL; // Full condition (WR_CLK)
reg RD_EMPTY; // Empty condition (RD_CLK)

async_fifo_fwft #(
.C_WIDTH(C_WIDTH), // Data bus width
.C_DEPTH(C_DEPTH), // Depth of the FIFO
// Local parameters
.C_REAL_DEPTH(C_REAL_DEPTH),
.C_DEPTH_BITS(C_DEPTH_BITS),
.C_DEPTH_P1_BITS(C_DEPTH_P1_BITS)
)
fwft (
.RD_CLK(RD_CLK), // Read clock
.RD_RST(RD_RST), // Read synchronous reset
.WR_CLK(WR_CLK), // Write clock
.WR_RST(WR_RST), // Write synchronous reset
.WR_DATA(WR_DATA), // Write data input (WR_CLK)
.WR_EN(WR_EN), // Write enable, high active (WR_CLK)
.RD_DATA(RD_DATA), // Read data output (RD_CLK)
.RD_EN(RD_EN), // Read enable, high active (RD_CLK)
.WR_FULL(WR_FULL), // Full condition (WR_CLK)
.RD_EMPTY(RD_EMPTY) // Empty condition (RD_CLK)
);

initial begin
RD_CLK = 0;
WR_CLK = 0;
RD_RST = 0;
WR_RST = 0;

WR_DATA = 15;

#23 WR_EN = 1;
RD_EN = 1;
end

always
#5 RD_CLK = !RD_CLK;

always
#7 WR_CLK = !WR_CLK;

endmodule


Guest

Wed Jan 31, 2018 3:13 pm   



On Wednesday, 31 January 2018 04:11:11 UTC+1, qq wrote:
Quote:
Why am I getting "./functions.vh:44: syntax error" for https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/functions.vh#L44 ?

My testbench file is as followed:


`timescale 1ns/1ns
`include "functions.vh"

module async_fifo_fwft_tb;

parameter C_WIDTH = 32; // Data bus width
snip


You cannot have functions outside modules...

Julio

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