EDAboard.com | EDAboard.de | EDAboard.co.uk | WTWH Media

verilog reg usage

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - FPGA - verilog reg usage

promach
Guest

Sat Apr 28, 2018 3:45 am   



Does <= (reg) changes value at the same clk posedge or the next clk posedge in simulation ?


Guest

Tue May 08, 2018 12:45 pm   



On Saturday, 28 April 2018 09:47:42 UTC+8, promach wrote:
> Does <= (reg) changes value at the same clk posedge or the next clk posedge in simulation ?

all of the usage of non-blocking assignment to a value (the type of it must be 'reg')in always block will lead to the value-changed in the next posedge or negedge of clk.

elektroda.net NewsGroups Forum Index - FPGA - verilog reg usage

Ask a question - edaboard.com

Arabic version Bulgarian version Catalan version Czech version Danish version German version Greek version English version Spanish version Finnish version French version Hindi version Croatian version Indonesian version Italian version Hebrew version Japanese version Korean version Lithuanian version Latvian version Dutch version Norwegian version Polish version Portuguese version Romanian version Russian version Slovak version Slovenian version Serbian version Swedish version Tagalog version Ukrainian version Vietnamese version Chinese version Turkish version
EDAboard.com map