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Verilog module in VHDL for Altera devices

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Martin Thompson
Guest

Wed Apr 06, 2016 7:44 pm   



KJ <kkjennings_at_sbcglobal.net> writes:

Quote:
On Tuesday, April 5, 2016 at 3:31:25 PM UTC-4, Rob Gaddi wrote:

The one limitation is that direct entity instantiation plays very
Verilogily with simulation. With a component declaration, if you
recompile the thing you're instantiating you can just restart the
simulation and go. With direct entities you have to recompile your way
everything back up the way.


That has not been my experience with direct entity instantiation. If I change something, I just recompile the file that changed and
go. If I change something on the entity, like add/remove a signal, then I also have to recompile the file(s) that instantiate that
entity. But that behavior I don't think is any different than if a component is declared.


If you have your entity and architecture in the same file (as many
people do), unless you can instruct the compiler to only compile the
architecture, you end up with the effect that is described (having to
recompile all the way up).

vcom -just b something.vhd

does the trick with Modelsim.
Cheers,
Martin

--
martin.j.thompson_at_trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Martin Thompson
Guest

Thu Apr 14, 2016 9:21 pm   



KJ <kkjennings_at_sbcglobal.net> writes:

Quote:

Interesting, but like I said, that has not been my experience. Except for unusual cases, I have entity/architecture in the same
file, I use direct entity instantiation and I use Modelsim. When I only change the architecture the steps are:
- Edit/Save
- Click in the GUI to compile out of date files (which results in that
one file getting compiled)


That may be the difference, the GUI Smile I tend to stick at the command
line and just recompile the bits I know I'm working on (if it's only a
couple of files) or run the Makefile which tends to compile everything.
I'll have to check out the GUI option (although it runs counter to my
ingrained habits of command-lining allt he time I can!)

Thanks,
Martin

--
martin.j.thompson_at_trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

KJ
Guest

Fri Apr 15, 2016 12:06 am   



On Thursday, April 14, 2016 at 11:21:09 AM UTC-4, Martin Thompson wrote:
Quote:
KJ writes:


Interesting, but like I said, that has not been my experience. Except for unusual cases, I have entity/architecture in the same
file, I use direct entity instantiation and I use Modelsim. When I only change the architecture the steps are:
- Edit/Save
- Click in the GUI to compile out of date files (which results in that
one file getting compiled)

That may be the difference, the GUI Smile I tend to stick at the command
line and just recompile the bits I know I'm working on (if it's only a
couple of files) or run the Makefile which tends to compile everything.
I'll have to check out the GUI option (although it runs counter to my
ingrained habits of command-lining allt he time I can!)

In that case, I would wager that the reason you're compiling files all the way to the top is due to the make file. I'm guessing that file is setup with dependency rules that if file X changes then you must also compile the parents/grandparents/etc of file X. The GUI is simply compiling the file(s) that have changed since the last compile, there is no notion of dependencies for this operation.


Kevin

Martin Thompson
Guest

Thu Apr 21, 2016 4:52 pm   



KJ <kkjennings_at_sbcglobal.net> writes:



Quote:
I'm guessing
that file is setup with dependency rules that if file X changes then
you must also compile the parents/grandparents/etc of file X.


Agreed. Make has no concept of design units within files or the ability
to only compile parts of the file. Make is not ideally suited to VHDL
work :)

Quote:
The GUI is simply compiling the file(s) that have changed since the last compile, there is no notion of dependencies for this
operation.


I'd go further - I think the GUI is only compiling *parts* of the file
(like I do from the command-line) as if it compiled the whole file, it
would recompile the entity which would then trigger an "upward flow" of
recompiles (which you are not observing).

Does the GUI compile show what commands it is executing anywhere?

Martin


--
martin.j.thompson_at_trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

HT-Lab
Guest

Thu Apr 21, 2016 10:13 pm   



On 21/04/2016 11:52, Martin Thompson wrote:
Quote:
KJ <kkjennings_at_sbcglobal.net> writes:



I'm guessing
that file is setup with dependency rules that if file X changes then
you must also compile the parents/grandparents/etc of file X.

Agreed. Make has no concept of design units within files or the ability
to only compile parts of the file. Make is not ideally suited to VHDL
work :)

The GUI is simply compiling the file(s) that have changed since the last compile, there is no notion of dependencies for this
operation.

I'd go further - I think the GUI is only compiling *parts* of the file
(like I do from the command-line) as if it compiled the whole file, it
would recompile the entity which would then trigger an "upward flow" of
recompiles (which you are not observing).

Does the GUI compile show what commands it is executing anywhere?


Transcript window?

Seriously, I assume you are using Modelsim project files? If so then I
would strongly recommend you switch to .do/.tcl files as it will make
your life a lot easier. If compilation takes a long time then you can
use vmake although I believe you need to switch back to the old library
format to use them (I might be wrong). Just add the win32pe directory to
your search path and you can use simple batch/bash/.. scripts to compile
and run your code. If you want to use some Tcl in your script then you
can use vsim -c -do "-do mycompile.tcl;quit -f" type of commands.

Hans
www.ht-lab.com

Quote:
Martin



Allan Herriman
Guest

Fri Apr 22, 2016 4:37 pm   



On Thu, 21 Apr 2016 17:13:03 +0100, HT-Lab wrote:

Quote:
On 21/04/2016 11:52, Martin Thompson wrote:
KJ <kkjennings_at_sbcglobal.net> writes:



I'm guessing that file is setup with dependency rules that if file X
changes then you must also compile the parents/grandparents/etc of
file X.

Agreed. Make has no concept of design units within files or the
ability to only compile parts of the file. Make is not ideally suited
to VHDL work :)

The GUI is simply compiling the file(s) that have changed since the
last compile, there is no notion of dependencies for this operation.

I'd go further - I think the GUI is only compiling *parts* of the file
(like I do from the command-line) as if it compiled the whole file, it
would recompile the entity which would then trigger an "upward flow" of
recompiles (which you are not observing).

Does the GUI compile show what commands it is executing anywhere?

Transcript window?

Seriously, I assume you are using Modelsim project files? If so then I
would strongly recommend you switch to .do/.tcl files as it will make
your life a lot easier. If compilation takes a long time then you can
use vmake although I believe you need to switch back to the old library
format to use them (I might be wrong). Just add the win32pe directory to
your search path and you can use simple batch/bash/.. scripts to compile
and run your code. If you want to use some Tcl in your script then you
can use vsim -c -do "-do mycompile.tcl;quit -f" type of commands.


How do you switch back to the old library format? I stopped using
makefiles with Modelsim once they put the entire library in a single
file. Version 10.1something I think it was.

Thanks,
Allan

Rob Gaddi
Guest

Fri Apr 22, 2016 6:38 pm   



HT-Lab wrote:

Quote:
On 22/04/2016 11:37, Allan Herriman wrote:
On Thu, 21 Apr 2016 17:13:03 +0100, HT-Lab wrote:

..


How do you switch back to the old library format? I stopped using
makefiles with Modelsim once they put the entire library in a single
file. Version 10.1something I think it was.

Thanks,
Allan

Hi Allan,

You could use "vlib -type directory" which will give you the older
(slower) format. I haven't used vmake for a while as I started to use
SystemC which for some reason is not supported by vmake,

Regards,
Hans.
www.ht-lab.com


You can also poke your modelsim.ini to make it the default.

[utils]
; Default Library Type (while creating a library with "vlib")
; 0 - legacy library using subdirectories for design units
; 2 - flat library
DefaultLibType = 0

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

HT-Lab
Guest

Fri Apr 22, 2016 8:02 pm   



On 22/04/2016 11:37, Allan Herriman wrote:
Quote:
On Thu, 21 Apr 2016 17:13:03 +0100, HT-Lab wrote:

...


How do you switch back to the old library format? I stopped using
makefiles with Modelsim once they put the entire library in a single
file. Version 10.1something I think it was.

Thanks,
Allan

Hi Allan,


You could use "vlib -type directory" which will give you the older
(slower) format. I haven't used vmake for a while as I started to use
SystemC which for some reason is not supported by vmake,

Regards,
Hans.
www.ht-lab.com

Allan Herriman
Guest

Sat Apr 23, 2016 2:34 pm   



On Fri, 22 Apr 2016 16:38:16 +0000, Rob Gaddi wrote:

Quote:
HT-Lab wrote:

On 22/04/2016 11:37, Allan Herriman wrote:
On Thu, 21 Apr 2016 17:13:03 +0100, HT-Lab wrote:

..


How do you switch back to the old library format? I stopped using
makefiles with Modelsim once they put the entire library in a single
file. Version 10.1something I think it was.

Thanks,
Allan

Hi Allan,

You could use "vlib -type directory" which will give you the older
(slower) format. I haven't used vmake for a while as I started to use
SystemC which for some reason is not supported by vmake,

Regards,
Hans.
www.ht-lab.com


You can also poke your modelsim.ini to make it the default.

[utils]
; Default Library Type (while creating a library with "vlib")
; 0 - legacy library using subdirectories for design units ; 2 - flat
library DefaultLibType = 0


Thanks Rob and Hans. I look forward to being able to use makefiles again.

Allan

Martin Thompson
Guest

Thu Apr 28, 2016 8:00 pm   



HT-Lab <hans64_at_htminuslab.com> writes:

Quote:
On 21/04/2016 11:52, Martin Thompson wrote:
Transcript window?

Seriously, I assume you are using Modelsim project files?


Nope.

Quote:
If so then I would
strongly recommend you switch to .do/.tcl files as it will make your life a lot
easier.


I do (!) use do files.

I have used Makefiles in the past, but compile time is much less of an
issue these days.

Cheers,
Martin

--
martin.j.thompson_at_trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

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