elektroda.net NewsGroups Forum Index - Verilog Language
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| Frequency detection | temo_aldorado | 1 / 68 | Thu Apr 28, 2011 4:37 pm rickman |
| Newbie Question on State Machines | jjlindula@hotmail.com | 6 / 194 | Thu Apr 28, 2011 4:11 pm Cary R. |
I'd rather switch than fight! [  Goto page: 1 ... 9, 10, 11 ] | rickman | 153 / 759 | Thu Apr 28, 2011 8:26 am Alan Fitch |
| pipeline code [ Goto page: 1, 2 ] | Chris Hinsley | 23 / 198 | Mon Apr 25, 2011 4:41 pm Mark Curry |
| Keep model output delay value | Essen | 2 / 70 | Sun Apr 24, 2011 3:25 pm Essen |
| GTKWave 3.2.0 for Windows is available | Muzaffer Kal | 12 / 243 | Sun Apr 17, 2011 7:25 am Muzaffer Kal |
| unused outputs ? | Chris Hinsley | 6 / 69 | Fri Apr 15, 2011 7:01 pm Gabor |
| need help regarding block ram in verilog | m2star | 1 / 58 | Fri Apr 08, 2011 3:43 pm johnp |
| SystemVerilog Array of Interfaces | Ari Ari | 3 / 142 | Fri Apr 08, 2011 7:04 am Steven Sharp |
| Using mopdorts within modports | Puneet Dhillon | 1 / 81 | Sun Mar 27, 2011 10:19 am Jonathan Bromley |
| regarding "posedge" [ Goto page: 1, 2, 3 ] | Amir | 42 / 255 | Tue Mar 22, 2011 10:59 am Jan Decaluwe |
| Successive approximation ADC | Rohit Vyas | 1 / 131 | Sat Mar 19, 2011 1:35 pm Jonathan Bromley |
| ERROR: Reference to vector reg 'InKbWd' is not a legal net l | Aldorus | 5 / 78 | Fri Mar 18, 2011 9:07 pm glen herrmannsfeldt |
| need a cheap student edition FPGA [ Goto page: 1 ... 89, 90, 91 ] | server | 1354 / 17545 | Fri Mar 18, 2011 3:06 pm gabor |
| `ifdef inside a macro | Andreas Ehliar | 1 / 106 | Fri Mar 18, 2011 1:51 pm Jonathan Bromley |
| Wow! No TestbenchWow! [ Goto page: 1, 2 ] | rickman | 15 / 222 | Tue Mar 15, 2011 11:29 pm Jonathan Bromley |
| LFSR 32-bit parity generator | Daku | 2 / 91 | Tue Mar 15, 2011 11:27 pm gabor |
| HI all please sort it out problem about block ram in verilog | m2star | 3 / 79 | Sun Mar 06, 2011 4:32 am gabor |
| include file problem in verilog plz sort it out ............ | m2star | 4 / 129 | Fri Mar 04, 2011 9:54 am m2star |
| Please help | raghu | 4 / 163 | Wed Mar 02, 2011 8:26 am m2star |
| Clarification required to do my Project | Pandiarajan | 3 / 109 | Tue Mar 01, 2011 9:32 pm mike |
| Most popular VHDL/Verilog | Philippe | 2 / 91 | Thu Feb 24, 2011 12:45 pm Stéphane Goujet |
| correct way to implement muxing of signals | googler | 2 / 75 | Mon Feb 21, 2011 10:16 pm gabor |
| Dynamic type in declarative context | Ronit Edri | 1 / 128 | Sun Feb 20, 2011 4:14 pm Jonathan Bromley |
| Open Source Verilog 2001 Synthesis Tool | parvez ahmad | 5 / 207 | Sun Feb 20, 2011 9:46 am nazia khan |
| I'd Rather Switch than Fight! | rickman | 3 / 78 | Thu Feb 17, 2011 1:12 am Andy |
| system verilog ques. Is there a separate newsgroup for syste | masoodtahir | 1 / 76 | Thu Feb 10, 2011 1:11 pm Marcus Harnisch |
| Have the errors in “HDL Chip Design” by Douglas Smith ever | Jan Decaluwe | 10 / 85 | Thu Feb 10, 2011 9:17 am Jan Decaluwe |
| $monitor and icarus (iverilog) | Aldorus | 2 / 94 | Thu Feb 10, 2011 1:29 am Aldorus |
| Verilog Book for VHDL Users [ Goto page: 1, 2 ] | rickman | 20 / 253 | Sat Jan 29, 2011 9:57 pm rickman |
| Verilog to state diagram | glen herrmannsfeldt | 1 / 166 | Mon Jan 24, 2011 9:47 pm Jonathan Bromley |
| sign extension in verilog | rekz | 10 / 118 | Thu Jan 20, 2011 2:49 am Aswin |
| hello sir, | prasanthi | 1 / 71 | Wed Jan 05, 2011 9:12 pm d_s_klein |
| Flatten Verilog netlist | Kenneth Brun Nielsen | 6 / 182 | Mon Jan 03, 2011 9:08 pm Kenneth Brun Nielsen |
| Bipolar Non-Return to Zero Encoder | Daku | 1 / 93 | Sun Jan 02, 2011 7:26 pm rickman |
| spacewire project on opencores.org | Alessandro Basili | 5 / 124 | Fri Dec 24, 2010 5:51 pm Paul Colin Gloster |
| Systemverilog synthesizable Parameterized interfaces with mo | vijay | 1 / 80 | Wed Dec 15, 2010 7:17 pm Jonathan Bromley |
| FPGA project structure definition | saar drimer | 7 / 112 | Tue Dec 07, 2010 12:31 am Pontus |
| questa file IO | Verictor | 1 / 109 | Thu Dec 02, 2010 5:19 am Muzaffer Kal |
| gtkwave-3.3.15 released | bybell | 2 / 92 | Tue Nov 30, 2010 6:14 pm bybell |
| System Verilog 2D input port? | John Smith | 1 / 114 | Thu Nov 25, 2010 6:29 am unfrostedpoptart |
| How to get SV to scale | Thomas Jones | 3 / 96 | Fri Nov 19, 2010 7:08 pm Mark Curry |
| 4 bit & 8 bit register comparison | Deepu | 3 / 164 | Thu Nov 04, 2010 9:52 pm Jonathan Bromley |
| a defined built-in method for parameters? | mag | 3 / 95 | Thu Oct 28, 2010 4:09 pm mag |
| Random Number Generator | Deepu | 4 / 123 | Tue Oct 26, 2010 2:30 am glen herrmannsfeldt |
| Command for running tf_and acc_ PLI routines | Taral Shah | 1 / 92 | Mon Oct 25, 2010 7:58 pm Cary R. |
| Need help in AUTO_TEMPLATE with backslash signal name | bitter | 1 / 85 | Fri Oct 22, 2010 5:11 am Guest |
| SVA for VHDL state machine | Verictor | 2 / 106 | Mon Oct 11, 2010 10:16 am hssig |
| ANN: Multi-port register-file (memory) generator | Nikolaos Kavvadias | 1 / 395 | Sat Oct 09, 2010 5:56 pm Leon |
| Assertin with delay (not clock cycles) | Deepu | 1 / 100 | Fri Oct 01, 2010 10:56 pm Jonathan Bromley |
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