Verilog declaration question

Fri Aug 12, 2011 9:23 am   

Could some Verilog guru please clarify the following ?
What is the difference between
input [10:5] a;
and
input [5:0] a;

Both are 6 bits wide. In which cases would one use
the first, as compared to the second ? Thanks in advance
for your help.

Fri Aug 12, 2011 8:00 pm   

99.9% of the time they will act the same. If you always deal with the whole signal, Verilog will hide the difference. If you need to index some of the bits within 'a', there will obviously be a difference. The LSB of the first is a[5] while the LSB of the second will be a[0]. In fact, you could even define it as [0:5] and it will work the same almost all the time, but most designers will look at you funny...

You would only do something like [10:5] if it represented a slice of a large vector and you wanted to keep the bit numbers the same.

David