Verilog Book for VHDL Users

On Jan 19, 5:49 am, Anssi Saari <a...@sci.fi> wrote:



rickman <gnu...@gmail.com> writes:
Searching here I found recommendations for "The Verilog® Hardware
Description Language", Donald E. Thomas and "HDL Programming
Fundamentals: VHDL and Verilog", Nazeih Botros.  The former appears to
be a bit long in the tooth and the latest edition (which is the only
one covering the 2001 revision of the standard) is quite pricey.  The
latter is another dual book comparing VHDL and Verilog side by side.
I don't know about its organization.

What do the Verilog users recommend in my case?  Why do you like the
books you like?

I don't know what to recommend, since I haven't used Verilog much
since 2002. I did buy Botros' book recently since it's so cheap and
includes a CD too with code examples and figures from the book. But I
mostly need a VHDL book and this one seems a little shallow so I find
myself relying on Ashenden's VHDL book mostly. I do beliece Botros'
book is the only book in print that covers both VHDL and Verilog.

When I was learning Verilog in the mid-1990s, I think I used Cadence's
excellent manuals for the old Verilog-XL and experienced colleagues.

I'm curious, why are you using VHDL more now?  Is this a job
requirement or do you prefer VHDL?  Was there something about Verilog
you didn't like?

As I am learning Verilog, I am finding that I had become pretty used
to VHDL and I had a certain level of comfort knowing that if I made a
dumb mistake, the tool would most likely let me know.  When I go
through the warning list with Verilog I see a number of things that
could easily trip me up.  I guess I'm nervous that I am going to be
bitten by one of these at some point.  I guess I'll keep checking the
warnings.

Rick

On Jan 19, 11:19 am, rickman <gnu...@gmail.com> wrote:

As I am learning Verilog, I am finding that I had become pretty used
to VHDL and I had a certain level of comfort knowing that if I made a
dumb mistake, the tool would most likely let me know.  When I go
through the warning list with Verilog I see a number of things that
could easily trip me up.  I guess I'm nervous that I am going to be
bitten by one of these at some point.  I guess I'll keep checking the
warnings.

One of the big "biters" in Verilog is the ability to declare a net
implicitly.
This often covers up a mistake in spelling.  There is even no warning
for implicitly declared nets unless they happen to cause a size
mismatch
at a module port (this would be an error in VHDL).  Verilog 2001 has
added the 'default_nettype directive which allows you to override this
behavior.  I generally do this at the top of each module:

`default_nettype none

module foo
. . .
And then this at the bottom:

endmodule

`default_nettype wire

Bringing the default back.  Note that as long as you only write your
own
code this bit at the end would make no difference, but as soon as you
add some IP from another source (Xilinx comes to mind) you can end
up with piles of errors when they use implicitly declared nets.

There are some things about Verilog that I think make it much more
human friendly like not requiring constants to be sized.  I go batty
reading VHDL case statements with all the cases listed in binary.
However, this can again show some lack of error coverage because
there is no check to see if the constant will even fit into the size
required by the operand.  For example:

reg [3:0] foo;

always @ (posedge clk)
  foo <= 25;

Obviously you can't fit 25 into a 4-bit register, but this won't even
cause
a warning, it just blithely takes the low 4 bits of the value and
stuffs it
into foo.

I'm curious, why are you using VHDL more now? Is this a job
requirement or do you prefer VHDL?

Was there something about Verilog you didn't like?

Was there something about Verilog you didn't like?

I liked it just fine for design. Didn't much care for writing
testbenches in it. Most of my Verilog work was for telecom. For

rickman <gnu...@gmail.com> writes:
I'm curious, why are you using VHDL more now?  Is this a job
requirement or do you prefer VHDL?  

Job requirement. Euroland is VHDLland too, with some exceptions.
Usually means customer is somewhere else, like in North America or
Asia. Even then, Verilog may be the result of autoconversion from
VHDL...

Was there something about Verilog you didn't like?

I liked it just fine for design. Didn't much care for writing
testbenches in it. Most of my Verilog work was for telecom. For
example, generating ATM cells and sending them to the design was just
awful. Should've done it in Perl and put the data in a file. In fact,
I did that for the received data.

I'm not too keen on VHDL, but it gets the job done. I used to hate the
strong typing and required conversions, but I guess I don't mind that
much any more. Maybe it's influence from my recent interest in Python
too.

On 1/15/2011 12:09 PM, rickman wrote:

This is starting to sound like VHDL...! I don't mind being explicit.
It is just that in VHDL it can get rather confusing as to what you
need to be explicit about or how exactly to be explicit.

I find it hard to believe that there are no good texts on this.

It is true.
I found this one slightly useful:http://www.google.com/search?q=botros+isbn+1584508558

It's the only book of side by side vhdl|verilog examples in print.
But that is all it is -- simple synthesis examples and a short
explanation. No language reference or simulation examples.
But it's a quick way for a vhdl guy to get started
on verilog synthesis, and the price is right.

-- Mike Treseler