verilog and runtime directive around continuous assignment

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sense
Guest

Fri Dec 09, 2011 12:08 am

Hi all,

I have a continuous assingment in verilog which I want to exclude in a
simulation under certain condition. Having a `ifdef `endif around the
code requires me to recompile and I cannot have a testplusarg around a
continuous assignment.

Any way to work around this problem?

Sagar

glen herrmannsfeldt
Guest

Fri Dec 09, 2011 12:36 am

sense <sagar.1986_at_gmail.com> wrote:

Quote:

I have a continuous assingment in verilog which I want to exclude in a
simulation under certain condition. Having a `ifdef `endif around the
code requires me to recompile and I cannot have a testplusarg around a
continuous assignment.

What do you want it to be when it isn't assigned?

Quote:

Any way to work around this problem?

How about

assign x = (condition) ? value : 8'hz;

That is, tristate based on condition. Though zero might
be a better choice.

-- glen

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