Joseph
Guest
Wed Jun 09, 2010 12:33 pm
Hi all,
I have been doing some development using Quartus.
In a counter process an integer variable has been declared and used.
The variable needs to be sent to the output which is a
STD_LOGIC_VECTOR. Using the numeric_std package how this can be
accomplished as I have some problems when it comes to type
conversions. I want to avoid using the _arith package.
Regards,
Joseph A. Zammit
Andy Rushton
Guest
Wed Jun 09, 2010 12:33 pm
Joseph wrote:
Quote:
Hi all,
I have been doing some development using Quartus.
In a counter process an integer variable has been declared and used.
The variable needs to be sent to the output which is a
STD_LOGIC_VECTOR. Using the numeric_std package how this can be
accomplished as I have some problems when it comes to type
conversions. I want to avoid using the _arith package.
Depending on whether you want the std_logic_vector to be signed or unsigned:
slv_out <= std_logic_vector(to_signed(integer_in));
or
slv_out <= std_logic_vector(to_unsigned(integer_in));
Quote:
Regards,
Joseph A. Zammit
Brian Drummond
Guest
Wed Jun 09, 2010 12:33 pm
On Wed, 09 Jun 2010 10:41:47 +0100, Andy Rushton <vfls_at_andyrushton.co.uk> wrote:
Quote:
Joseph wrote:
Hi all,
I have been doing some development using Quartus.
In a counter process an integer variable has been declared and used.
The variable needs to be sent to the output which is a
STD_LOGIC_VECTOR. Using the numeric_std package how this can be
accomplished as I have some problems when it comes to type
conversions. I want to avoid using the _arith package.
Depending on whether you want the std_logic_vector to be signed or unsigned:
slv_out <= std_logic_vector(to_signed(integer_in));
or
slv_out <= std_logic_vector(to_unsigned(integer_in));
or
slv_out <= std_logic_vector(to_unsigned(integer_in, slv_out'length));
- Brian
Tricky
Guest
Wed Jun 09, 2010 1:32 pm
On 9 June, 10:33, Joseph <joz...@gmail.com> wrote:
Quote:
Hi all,
I have been doing some development using Quartus.
In a counter process an integer variable has been declared and used.
The variable needs to be sent to the output which is a
STD_LOGIC_VECTOR. Using the numeric_std package how this can be
accomplished as I have some problems when it comes to type
conversions. I want to avoid using the _arith package.
Regards,
Joseph A. Zammit
Why not just change the output port to be an integer (assuming its not
a top level port)?
