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UVVM (Universal VHDL Verification Methodology) goes Open Sou

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elektroda.net NewsGroups Forum Index - VHDL Language - UVVM (Universal VHDL Verification Methodology) goes Open Sou


Guest

Tue Jan 26, 2016 12:42 pm   



UVVM Utility Library has always been open source. UVVM VVC Framework (VVC=VHDL Verification Component) on the other hand has so far only been available as encrypted Freeware, but is as of today released as open source - free and with no encryption. This means the complete UVVM is now open source.

UVVM Utility Library (previously Bitvis Utility Library) is a basic VHDL testbench infrastructure that allows a much faster testbench development with a good logging and alert handling mechanism, topped with lots of useful checking procedures - like checking a signal value, stability and change. It also has lots of support for string handling and BFMs, and a simple, but efficient set of functions for random value generation.
UVVM Utility Library is dead easy to use. The extremely low user threshold allows users to be up and running in less than an hour.
This previous post on LinkedIn will give you some more info on why you should use this library.

UVVM VVC Framework is a VHDL Verification Component system that allows multiple interfaces on a DUT to be stimulated/handled simultaneously in a very structured manner, and controlled by a very simple to understand software like test sequencer.
VVC Framework is unique as an open source VHDL approach to building a structured testbench architecture using Verification components and a simple protocol to access these. As an example a simple command like uart_expect(UART_VVCT, my_data), or axilite_write(AXILITE_VVCT, my_addr, my_data, my_message) will automatically tell the respective VVC (for UART or AXI-Lite) to execute the uart_receive() or axilite_write() BFM respectively. The really great benefit here is that these commands may be issued at the same time from the test sequencer - thus allowing full control of when an access is to be performed, and the commands are understandable "even" for a software developer Wink The commands may be queued, skewed, delayed, synchronised, etc - and a super-set for applying constrained random or other sequences of data may of of course also be applied.
This yields an excellent control over your testbench and VVCs.
For debugging you can select logging of a command when it is issued from the sequencer, when it is received by the VVC, when it is initiated by the VVC and/or when it has been executed towards the DUT. This allows full overview of all actions in your complete testbench.
This previous post on LinkedIn will give you some more info on why you should use this library.

Utility Library may be used stand-alone for simple testbenches, whereas VVC Framework uses the Utility Library for logging, alert handling and checkers.

The UVVM libraries may be downloaded from GitHub (https://github.com/UVVM) or from Bitvis (http://bitvis.no/products/uvvm-vvc-framework/).

Gabor Szakacs
Guest

Tue Feb 02, 2016 8:30 am   



On 1/26/2016 5:42 AM, espen.tallaksen_at_bitvis.no wrote:
Quote:
UVVM Utility Library has always been open source.


One more layer of nested acronym:

VHSIC = Very High Speed Integrated Circuit (old DARPA project)
VHDL = VHSIC Hardware Description Language
UVVM = Universal VHDL Verification Methodology

--
Gabor

Stef
Guest

Tue Feb 02, 2016 5:39 pm   



On 2016-02-02 Gabor Szakacs wrote in comp.lang.vhdl:
Quote:
On 1/26/2016 5:42 AM, espen.tallaksen_at_bitvis.no wrote:
UVVM Utility Library has always been open source.


One more layer of nested acronym:

VHSIC = Very High Speed Integrated Circuit (old DARPA project)
VHDL = VHSIC Hardware Description Language
UVVM = Universal VHDL Verification Methodology


Or, after pre-processing:

UVVM = Universal Very High Speed Integrated Circuit Hardware Description Language Verification Methodology


--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

Crazee Edeee, his prices are INSANE!!!

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