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UVM on FPGA

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Guest

Mon Jan 07, 2019 8:45 am   



Hi all,
Can UVM code dumped on FPGA .Does UVM TB can synthesized.

Regards
DARSHAN

Kevin Neilson
Guest

Tue Jan 08, 2019 11:45 am   



On Sunday, January 6, 2019 at 11:50:22 PM UTC-7, kadarsh...@gmail.com wrote:
Quote:
Hi all,
Can UVM code dumped on FPGA .Does UVM TB can synthesized.

Regards
DARSHAN


No.

HT-Lab
Guest

Tue Jan 08, 2019 9:45 pm   



On 08/01/2019 10:26, Kevin Neilson wrote:
Quote:
On Sunday, January 6, 2019 at 11:50:22 PM UTC-7, kadarsh...@gmail.com wrote:
Hi all,
Can UVM code dumped on FPGA .Does UVM TB can synthesized.

Regards
DARSHAN

No.

Moving your testbench onto hardware is not new and is being used by many
companies. You will find that high-end synthesis tools, P&R vendors and
some custom tools will give you access to synthesizable modules like bus
checkers, protocol checkers, random number generators, traffic analysers
etc which can be used to build an on-chip testbench. In addition PSL/SVA
and some OVL monitor can be synthesised as well.

So Kevin is right that UVM cannot be synthesised out of the box but if
simulation is too slow and you can't afford an emulator then moving your
testbench on-chip is not a bad idea. In addition most simulator are
faster on synthesizable code so trying to keep your testbench
synthesizable might improve simulation speed.

Good luck,
Hans.
www.ht-lab.com

elektroda.net NewsGroups Forum Index - Verilog Language - UVM on FPGA

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