stevem1
Guest
Fri Jul 08, 2011 7:47 am
I am modeling some bus control signals that need to change after a
rising master clock.
I control these signals from inside a task that I call from the main
testbench. I call this
task asynchronous to the master clock, so I put a wait (CLK) statement
inside the task
and before I modify any control signals, in order to synchronize the
control signals to the master clock.
This kindof works but the control signals are changing after the
positive and negative
edges of the clock.
So maybe you can't use a "wait (CLK)" inside a task. It appears that
you can only use a "wait (CLK)"
inside an "always" statement or an "initial" statemnet. Is this
correct ?
If so, then I need to do the synchronization outside of the task, and
at the test bench level, before
calling the task. This isn't obvious reading the LRM.
-steve
johnp
Guest
Fri Jul 08, 2011 2:11 pm
On Jul 7, 10:47 pm, stevem1 <steve.martind...@gmail.com> wrote:
Quote:
I am modeling some bus control signals that need to change after a
rising master clock.
I control these signals from inside a task that I call from the main
testbench. I call this
task asynchronous to the master clock, so I put a wait (CLK) statement
inside the task
and before I modify any control signals, in order to synchronize the
control signals to the master clock.
This kindof works but the control signals are changing after the
positive and negative
edges of the clock.
So maybe you can't use a "wait (CLK)" inside a task. It appears that
you can only use a "wait (CLK)"
inside an "always" statement or an "initial" statemnet. Is this
correct ?
If so, then I need to do the synchronization outside of the task, and
at the test bench level, before
calling the task. This isn't obvious reading the LRM.
-steve
Don't use wait, use @(posedge CLK) ;
John Providenza
Jonathan Bromley
Guest
Sat Jul 09, 2011 6:23 pm
On Thu, 7 Jul 2011 22:47:26 -0700 (PDT), stevem1 wrote:
Quote:
I am modeling some bus control signals that need to change after a
rising master clock.
I control these signals from inside a task that I call from the main
testbench. I call this
task asynchronous to the master clock, so I put a wait (CLK) statement
inside the task
and before I modify any control signals, in order to synchronize the
control signals to the master clock.
Fair enough, although wait(CLK) probably doesn't do
exactly what you want.
Quote:
This kindof works but the control signals are changing after the
positive and negative edges of the clock.
That makes little sense to me. Without more information
about your code it's impossible to guess what's happening.
Quote:
So maybe you can't use a "wait (CLK)" inside a task. It appears that
you can only use a "wait (CLK)"
inside an "always" statement or an "initial" statemnet. Is this
correct ?
No, it's not correct. You can prefix any procedural
statement with wait(), whether or not it's inside a task.
However, there's a standard "gotcha" associated with waiting
for any value-change in a task...
** it makes no sense to wait for value-changes
** on your task's arguments
because those arguments are a snapshot (copy) taken at
the moment your task is called, and they won't change
during the life of the task. This contrasts with
signal-class arguments to procedures in VHDL, which
are effectively references to a signal, so you *can*
see value-changes on them during the procedure's
execution.
As johnp pointed out, it's more likely to be useful
to wait by using @posedge(CLK). But again you must
be sure that CLK is a signal declared at the module
level, NOT an argument to the task - otherwise, the
@posedge will never trip.
SystemVerilog's "ref" arguments change the game here,
but perhaps it's best to stick with vanilla Verilog
while you're getting up to speed.
--
Jonathan Bromley
