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User Defined Primitives

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Guest

Sat Jul 01, 2017 9:10 pm   



I'm just learning Verilog now and came across User Defined Primitives in my textbook. They seem really useless to me because they can only have 1 output. What is the use of them if you can only have 1 output? Also do people use them a lot in development instead of modules?

Gabor
Guest

Sun Jul 02, 2017 6:29 pm   



On Saturday, 7/1/2017 3:10 PM, tylerjoshuahilbert_at_gmail.com wrote:
Quote:
I'm just learning Verilog now and came across User Defined Primitives in my textbook. They seem really useless to me because they can only have 1 output. What is the use of them if you can only have 1 output? Also do people use them a lot in development instead of modules?


(setting follow-up to c.a.verilog)

As this is a Verilog question, it makes sense to post in
comp.lang.verilog rather than the VHDL group.

My guess is that User Defined Primitives are not used very often,
but when they are it's more likely in ASIC design than FPGA design.
In my FPGA work I don't use either the pre-defined primitives or
user defined primitives, since the tools are very good at inferring
logic from a behavioral description.

--
Gabor

elektroda.net NewsGroups Forum Index - VHDL Language - User Defined Primitives

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